[PATCH] riscv/kvm: Only context-switch senvcfg where it exists

[Anup Patel]

On Sat, Oct 10, 2026 at 10:23 AM Samuel Holland
<samuel.holland at sifive.com> wrote:
>
> Hi Anup,
>
> On 2026-10-09 9:23 PM, Anup Patel wrote:
> > On Thu, Aug 27, 2026 at 11:12 PM Davidlohr Bueso <dave at stgolabs.net> wrote:
> >>
> >> senvcfg arrived in privileged spec 1.12, but H-capable cores on a
> >> 1.11 base exist, ie: sifive P500 (ESWIN EIC7700X) implements the
> >> hypervisor extension yet has no senvcfg. KVM swaps the CSR
> >> unconditionally on every vCPU entry, panicing the host upon a guest
> >> executing its first instruction:
> >>
> >>   Oops - illegal instruction [#1]
> >>   Modules linked in: kvm
> >>   CPU: 2 UID: 0 PID: 127 Comm: qemu-system-ris Not tainted 7.2.0-kvm73bug+ #4 PREEMPTLAZY
> >>   Hardware name: Unknown Unknown Product/Unknown Product, BIOS 2024.01 01/01/2024
> >>   epc : kvm_riscv_vcpu_enter_exit+0x26/0xcf8 [kvm]
> >>    ra : kvm_arch_vcpu_ioctl_run+0x4ce/0x5a6 [kvm]
> >>   status: 0000000200000100 badaddr: 0000000010a797f3 cause: 0000000000000002
> >>   [<ffffffff01df432e>] kvm_riscv_vcpu_enter_exit+0x26/0xcf8 [kvm]
> >>   [<ffffffff01deb3b0>] kvm_arch_vcpu_ioctl_run+0x4ce/0x5a6 [kvm]
> >>   [<ffffffff01dd7914>] kvm_vcpu_ioctl+0x180/0x5e4 [kvm]
> >>   [<ffffffff8025702e>] __riscv_sys_ioctl+0x84/0x9a
> >>   [<ffffffff80dfdc72>] do_trap_ecall_u+0x1d8/0x38a
> >>   [<ffffffff80e08644>] handle_exception+0x168/0x174
> >>   Code: 84aa 892e b703 8887 1773 1067 3023 16e5 b783 8907 (97f3) 10a7
> >>
> >> Touch the CSR only when RISCV_ISA_EXT_XLINUXENVCFG is set, similar
> >> to __switch_to_envcfg() as well as other swaps conditional on
> >> their extentions.
> >>
> >> Fixes: db3c01c7a308 ("RISCV: KVM: Add senvcfg context save/restore")
> >> Signed-off-by: Davidlohr Bueso <dave at stgolabs.net>
> >
> > Your patch is only checking RISCV_ISA_EXT_XLINUXENVCFG when
> > saving/restoring senvcfg but not checking RISCV_ISA_EXT_XLINUXENVCFG
> > when accessing henvcfg. This tells me that P500 somehow manages to
> > implement henvcfg but forgot to implement senvcfg. Clearly, checking
> > RISCV_ISA_EXT_XLINUXENVCFG is not the right approach.
>
> As the other replies have mentioned, this generation of P550 does not implement
> henvcfg either. I believe checking RISCV_ISA_EXT_XLINUXENVCFG would be
> sufficient here. The only concern is that riscv,isa-extensions = "h"
> specifically references ISA version 20211203, which includes Ss1p12, so
> RISCV_ISA_EXT_H should imply RISCV_ISA_EXT_XLINUXENVCFG.

Yes, this was my next comment as well. Presence of H-extension should
imply XLINUXENVCFG due henvcfg CSR.

>
> > Instead, I suggest introducing static-key kvm_riscv_no_senvcfg and set
> > it only for P500 (ESWIN EIC7700X) in kvm_riscv_setup_vendor_features().
> > Also, don't save/restore senvcfg CSR only when kvm_riscv_no_senvcfg is
> > set.
>
> Or maybe we should add a new riscv,isa-extensions = "h0p6" or similar. This
> would not imply RISCV_ISA_EXT_XLINUXENVCFG but would otherwise be the same the
> same as "h".

Its not like we will have more RISC-V CPUs with H-extension v0.6 so
let's not introduce synthetic "h0p6" isa extension.

I think having static-key kvm_riscv_no_xenvcfg is much cleaner
because we already have kvm_riscv_vsstage_tlb_no_gpa which
is another work-around. The kvm_riscv_no_xenvcfg will be diabled
by default and will be enabled only for P500 (ESWIN EIC7700X).

Regards,
Anup