[kvm-unit-tests PATCH v2 0/8] riscv: ACPI boot and BRS-I SBI tests

[Xiang W]

This series lets RISC-V kvm-unit-tests boot on BRS-I platforms that
describe the system with UEFI + ACPI instead of a device tree, and adds
a first unit test for the SBI rules in the RISC-V Boot and Runtime
Services specification [1].

The RISC-V port currently assumes a DT for CPU bring-up, timer
frequency, ISA-string parsing and console setup. BRS-I firmware
typically does not provide a usable DT, and often has no MMIO UART
either. Without these changes the existing tests abort in setup before
they can exercise SBI.

Patches 1-4 teach the RISC-V library to initialize from ACPI when a DT
is absent:

- locate the ACPI 2.0 RSDP via the EFI configuration table
- parse MADT RINTC entries for hart / CPU bring-up
- read the timebase frequency from RHCT
- parse the ISA string from RHCT Hart Info nodes (match by ACPI UID)

Patch 5 prefers the SBI DBCN console when available and falls back to
the UART path otherwise, so ACPI guests without an MMIO UART can still
print. Patch 6 drops the early exit in the EFI runner that previously
rejected EFI_USE_ACPI=y.

Patch 7 moves isa_init() into cpu_init() so that every hart's ISA
extensions are parsed once the CPU list is known, rather than only for
the hart that first reaches thread_info_init().

Patch 8 adds riscv-brs, a unit test that checks the SBI requirements
from the BRS specification (version, HSM, TIME/Sstc, IPI/IMSIC,
RFENCE/IMSIC, PMU/Sscsrind+Ssccfg, and DBCN when SPCR type is 0x15).

v2 changes:
- Address review comments from Andrew Jones
- Prefer SBI DBCN with UART fallback instead of making SBI console
  exclusive (patch 5)
- Initialize ISA extensions for all harts in cpu_init (new patch 7)
- Check Ssaia + S-level IMSIC presence for the IPI/RFENCE skip
  conditions, and note the M-mode extension limitation for PMU

Tested with QEMU virt:

  EFI_USE_ACPI=y EFI_UEFI=/path/to/RISCV_VIRT_CODE.fd \
    ./riscv/efi/run riscv/riscv-brs.efi

[1] https://github.com/riscv-non-isa/riscv-brs

Xiang W (8):
  riscv: Initialize the ACPI RSDP from the EFI system table
  riscv: Add ACPI support for CPU initialization
  riscv: Add ACPI support for timer frequency discovery
  riscv: Add ACPI support for ISA string discovery
  riscv: Prefer SBI DBCN console with UART fallback
  riscv: efi: Allow ACPI boots
  riscv: initialize ISA extensions for all harts in cpu_init
  riscv: Add BRS SBI requirement tests

 lib/acpi.h                |  64 ++++++++-
 lib/riscv/asm/isa.h       |   3 +
 lib/riscv/asm/processor.h |   1 +
 lib/riscv/asm/sbi.h       |   2 +
 lib/riscv/io.c            |  41 +++---
 lib/riscv/isa.c           |  93 +++++++++++--
 lib/riscv/processor.c     |   1 -
 lib/riscv/setup.c         |  59 +++++++++
 lib/riscv/timer.c         |  38 ++++--
 riscv/Makefile            |   1 +
 riscv/efi/run             |   5 -
 riscv/riscv-brs.c         | 265 ++++++++++++++++++++++++++++++++++++++
 riscv/unittests.cfg       |   4 +
 13 files changed, 532 insertions(+), 45 deletions(-)
 create mode 100644 riscv/riscv-brs.c

-- 
2.47.3