[PATCH v4 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This series was applied to riscv/linux.git (fixes)
by Joerg Roedel <joerg.roedel at amd.com>:

On Tue, 12 May 2026 15:41:40 +0800 you wrote:
> From: Fangyu Yu <fangyu.yu at linux.alibaba.com>
> 
> RISC-V Svpbmt adds page-based memory types (PBMT) to PTEs, allowing
> mappings to be tagged as e.g. normal memory, non-cacheable memory, or
> I/O.
> 
> This series wires the RISC-V IOMMU Svpbmt capability into generic_pt
> and uses PBMT to encode device memory attributes for IOMMU mappings.
> 
> [...]

Here is the summary with links:
  - [v4,1/2] iommu/riscv: Advertise Svpbmt support to generic page table
    https://git.kernel.org/riscv/c/f196a8668797
  - [v4,2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
    (no matching commit)

You are awesome, thank you!
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