[PATCH v3] RISC-V: KVM: Zicbo[m|z|p] block sizes should be always present in ONE_REG

[Anup Patel]

On Mon, Jul 6, 2026 at 11:45 PM Anup Patel <anup.patel at oss.qualcomm.com> wrote:
>
> All config and core registers of the KVM RISC-V ONE_REG interface are
> expected to be always available to the KVM user-space and the KVM
> get-reg-list selftest assumes these registers to be as base registers.
>
> Currently, the Zicbo[m|z|p] block size config registers are only
> available when corresponding ISA extension is present on the host
> which breaks the above expectation. In fact, KVM get-reg-list selftest
> fails when any of the Zicbo[m|z|p] ISA extension is not present on
> host. To address this issue, drop the ISA extension checks from
> kvm_riscv_vcpu_get/set_reg_config() and copy_config_reg_indices()
> functions.
>
> Fixes: 031f9efafc08 ("KVM: riscv: Add KVM_GET_REG_LIST API support")
> Fixes: a044ef71043e ("RISC-V: KVM: use ENOENT in *_one_reg() when extension is unavailable")
> Fixes: 48e2febcda74 ("RISC-V: KVM: Provide UAPI for Zicbop block size")
> Fixes: cf05b059d59f ("RISC-V: KVM: Introduce common kvm_riscv_isa_check_host()")
> Signed-off-by: Anup Patel <anup.patel at oss.qualcomm.com>

Queued this patch as a fix for Linux-7.2-rcX

Thanks,
Anup

> ---
> Changes since v2:
>  - Update kvm_riscv_vcpu_set_reg_config() to return -EINVAL
>    only when value is non-zero and does not match underlying
>    host cache block size.
> Changes since v1:
>  - Update kvm_riscv_vcpu_set_reg_config() to return -EINVAL
>    only when Zicbo[m|z|p] ISA extension is enabled for VCPU
> ---
>  arch/riscv/kvm/vcpu_onereg.c | 38 ++++++------------------------------
>  1 file changed, 6 insertions(+), 32 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index bb920e8923c9..61988382570f 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -50,19 +50,13 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
>                 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
>                 break;
>         case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> -               if (kvm_riscv_isa_check_host(ZICBOM))
> -                       return -ENOENT;
> -               reg_val = riscv_cbom_block_size;
> +               reg_val = (kvm_riscv_isa_check_host(ZICBOM)) ? 0 : riscv_cbom_block_size;
>                 break;
>         case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
> -               if (kvm_riscv_isa_check_host(ZICBOZ))
> -                       return -ENOENT;
> -               reg_val = riscv_cboz_block_size;
> +               reg_val = (kvm_riscv_isa_check_host(ZICBOZ)) ? 0 : riscv_cboz_block_size;
>                 break;
>         case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
> -               if (kvm_riscv_isa_check_host(ZICBOP))
> -                       return -ENOENT;
> -               reg_val = riscv_cbop_block_size;
> +               reg_val = (kvm_riscv_isa_check_host(ZICBOP)) ? 0 : riscv_cbop_block_size;
>                 break;
>         case KVM_REG_RISCV_CONFIG_REG(mvendorid):
>                 reg_val = vcpu->arch.mvendorid;
> @@ -144,21 +138,15 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
>                 }
>                 break;
>         case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> -               if (kvm_riscv_isa_check_host(ZICBOM))
> -                       return -ENOENT;
> -               if (reg_val != riscv_cbom_block_size)
> +               if (reg_val && reg_val != riscv_cbom_block_size)
>                         return -EINVAL;
>                 break;
>         case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
> -               if (kvm_riscv_isa_check_host(ZICBOZ))
> -                       return -ENOENT;
> -               if (reg_val != riscv_cboz_block_size)
> +               if (reg_val && reg_val != riscv_cboz_block_size)
>                         return -EINVAL;
>                 break;
>         case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
> -               if (kvm_riscv_isa_check_host(ZICBOP))
> -                       return -ENOENT;
> -               if (reg_val != riscv_cbop_block_size)
> +               if (reg_val && reg_val != riscv_cbop_block_size)
>                         return -EINVAL;
>                 break;
>         case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> @@ -614,20 +602,6 @@ static int copy_config_reg_indices(const struct kvm_vcpu *vcpu,
>                 u64 size;
>                 u64 reg;
>
> -               /*
> -                * Avoid reporting config reg if the corresponding extension
> -                * was not available.
> -                */
> -               if (i == KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) &&
> -                   kvm_riscv_isa_check_host(ZICBOM))
> -                       continue;
> -               else if (i == KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) &&
> -                        kvm_riscv_isa_check_host(ZICBOZ))
> -                       continue;
> -               else if (i == KVM_REG_RISCV_CONFIG_REG(zicbop_block_size) &&
> -                        kvm_riscv_isa_check_host(ZICBOP))
> -                       continue;
> -
>                 size = IS_ENABLED(CONFIG_32BIT) ? KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
>                 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CONFIG | i;
>
> --
> 2.43.0
>