[PATCH v5 05/17] riscv: Add Zicclsm to cpufeature and hwprobe

[Paul Walmsley]

On Wed, 1 Jul 2026, Guodong Xu wrote:

> From: Jesse Taube <jesse at rivosinc.com>
> 
> Zicclsm requires misaligned support for all regular load and store
> instructions, both scalar and vector, but not AMOs or other
> specialized forms of memory access, to main memory regions with both
> the cacheability and coherence PMAs, as defined in the profiles spec.
> Even though mandated, misaligned loads and stores might execute
> extremely slowly. Standard software distributions should assume their
> existence only for correctness, not for performance.
> 
> Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
> Reviewed-by: Andy Chiu <andy.chiu at sifive.com>
> Reviewed-by: Charlie Jenkins <charlie at rivosinc.com>
> Tested-by: Charlie Jenkins <charlie at rivosinc.com>
> Signed-off-by: Jesse Taube <jesse at rivosinc.com>
> [Rebased, rewrote doc text, minor commit message revisions]
> Signed-off-by: Andrew Jones <andrew.jones at oss.qualcomm.com>
> Signed-off-by: Guodong Xu <docular.xu at gmail.com>

Thanks, queued for v7.3.


- Paul