[kvm-unit-tests v3 2/2] riscv: Add ISA double trap extension testing

[Andrew Jones]

On Thu, Jun 19, 2025 at 09:59:47AM +0200, Clément Léger wrote:
> 
> 
> On 16/06/2025 13:59, Clément Léger wrote:
> > This test allows to test the double trap implementation of hardware as
> > well as the SBI FWFT and SSE support for double trap. The tests will try
> > to trigger double trap using various sequences and will test to receive
> > the SSE double trap event if supported.
> > 
> > It is provided as a separate test from the SBI one for two reasons:
> > - It isn't specifically testing SBI "per se".
> > - It ends up by trying to crash into in M-mode.
> > 
> > Currently, the test uses a page fault to raise a trap programatically.
> > Some concern was raised by a github user on the original branch [1]
> > saying that the spec doesn't mandate any trap to be delegatable and that
> > we would need a way to detect which ones are delegatable. I think we can
> > safely assume that PAGE FAULT is delegatable and if a hardware that does
> > not have support comes up then it will probably be the vendor
> > responsibility to provide a way to do so.
> > 
> > Link: https://github.com/clementleger/kvm-unit-tests/issues/1 [1]
> > Signed-off-by: Clément Léger <cleger at rivosinc.com>
> > ---
> >  riscv/Makefile            |   1 +
> >  lib/riscv/asm/csr.h       |   1 +
> >  lib/riscv/asm/processor.h |  10 ++
> >  riscv/isa-dbltrp.c        | 210 ++++++++++++++++++++++++++++++++++++++
> >  riscv/unittests.cfg       |   4 +
> >  5 files changed, 226 insertions(+)
> >  create mode 100644 riscv/isa-dbltrp.c
> > 
> > diff --git a/riscv/Makefile b/riscv/Makefile
> > index 11e68eae..d71c9d2e 100644
> > --- a/riscv/Makefile
> > +++ b/riscv/Makefile
> > @@ -14,6 +14,7 @@ tests =
> >  tests += $(TEST_DIR)/sbi.$(exe)
> >  tests += $(TEST_DIR)/selftest.$(exe)
> >  tests += $(TEST_DIR)/sieve.$(exe)
> > +tests += $(TEST_DIR)/isa-dbltrp.$(exe)
> >  
> >  all: $(tests)
> >  
> > diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h
> > index 3e4b5fca..6a8e0578 100644
> > --- a/lib/riscv/asm/csr.h
> > +++ b/lib/riscv/asm/csr.h
> > @@ -18,6 +18,7 @@
> >  
> >  #define SR_SIE			_AC(0x00000002, UL)
> >  #define SR_SPP			_AC(0x00000100, UL)
> > +#define SR_SDT			_AC(0x01000000, UL) /* Supervisor Double Trap */
> >  
> >  /* Exception cause high bit - is an interrupt if set */
> >  #define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
> > diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h
> > index 631ce226..a3dab064 100644
> > --- a/lib/riscv/asm/processor.h
> > +++ b/lib/riscv/asm/processor.h
> > @@ -50,6 +50,16 @@ static inline void ipi_ack(void)
> >  	csr_clear(CSR_SIP, IE_SSIE);
> >  }
> >  
> > +static inline void local_dlbtrp_enable(void)
> > +{
> > +	csr_set(CSR_SSTATUS, SR_SDT);
> > +}
> > +
> > +static inline void local_dlbtrp_disable(void)
> > +{
> > +	csr_clear(CSR_SSTATUS, SR_SDT);
> > +}
> > +
> >  void install_exception_handler(unsigned long cause, void (*handler)(struct pt_regs *));
> >  void install_irq_handler(unsigned long cause, void (*handler)(struct pt_regs *));
> >  void do_handle_exception(struct pt_regs *regs);
> > diff --git a/riscv/isa-dbltrp.c b/riscv/isa-dbltrp.c
> > new file mode 100644
> > index 00000000..dcfa66da
> > --- /dev/null
> > +++ b/riscv/isa-dbltrp.c
> > @@ -0,0 +1,210 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * SBI verification
> > + *
> > + * Copyright (C) 2025, Rivos Inc., Clément Léger <cleger at rivosinc.com>
> > + */
> > +#include <alloc.h>
> > +#include <alloc_page.h>
> > +#include <libcflat.h>
> > +#include <stdlib.h>
> > +
> > +#include <asm/csr.h>
> > +#include <asm/page.h>
> > +#include <asm/processor.h>
> > +#include <asm/ptrace.h>
> > +#include <asm/sbi.h>
> > +
> > +#include <sbi-tests.h>
> > +
> > +static bool double_trap;
> > +static bool clear_sdt;
> > +
> > +#define INSN_LEN(insn)			((((insn) & 0x3) < 0x3) ? 2 : 4)
> 
> This macro should be removed since it was merged in another file.

Actually it should be removed since it's unused. If it was used, then we'd
need to rename the callsites since we call it RV_INSN_LEN.

I've removed it while applying to riscv/sbi.

https://gitlab.com/jones-drew/kvm-unit-tests/-/commits/riscv/sbi

Thanks,
drew