[kvm-unit-tests v3 0/2] riscv: Add double trap testing

[Clément Léger]

Add a test that triggers double trap and verify that it's behavior
conforms to the spec. Also use SSE to verify that an SSE event is
correctly sent upon double trap.

In order to run this test, one can use the following command using an
upstream version of OpenSBI:

$ QEMU=qemu-system-riscv64 \
  FIRMWARE_OVERRIDE=<opensbi>/fw_dynamic.bin \
  ./riscv-run riscv/isa-dbltrp.flat

---

v3:
 - Return an error only if SSE event wasn't unregistered successfully

v2:
 - Use WRITE_ONCE/READ_ONCE for shared variables
 - Remove locking flag for last test
 - Fix a few typos
 - Skip crash test if env var DOUBLE_TRAP_TEST_CRASH isn't set
 - Skip crash test if SSE event unregistering failed
 - Remove SDT clearing patch
 - Fix wrong check using ret.value nstead of ret.error

Clément Léger (2):
  lib/riscv: export FWFT functions
  riscv: Add ISA double trap extension testing

 riscv/Makefile            |   1 +
 lib/riscv/asm/csr.h       |   1 +
 lib/riscv/asm/processor.h |  10 ++
 lib/riscv/asm/sbi.h       |   5 +
 lib/riscv/sbi.c           |  20 ++++
 riscv/isa-dbltrp.c        | 210 ++++++++++++++++++++++++++++++++++++++
 riscv/sbi-fwft.c          |  49 +++------
 riscv/unittests.cfg       |   4 +
 8 files changed, 265 insertions(+), 35 deletions(-)
 create mode 100644 riscv/isa-dbltrp.c

-- 
2.49.0