[PATCH] RISC-V: KVM: Using user-mode pte within kvm_riscv_gstage_ioremap

[Radim Krčmář]

2025-08-09T11:20:20+08:00, <fangyu.yu at linux.alibaba.com>:
>>> From: Fangyu Yu <fangyu.yu at linux.alibaba.com>
>>> According to the RISC-V Privileged Architecture Spec, for G-stage address
>>> translation, all memory accesses are considered to be user-level accesses
>>> as though executed in Umode.
>>
>>What implementation are you using?  I would have assume that the
>>original code was tested on QEMU, so we might have a bug there.
>>
>
> This issue can be reproduced using QEMU.
> Since kvm has registered the MMIO Bus for IMSIC gpa, when a guest
> page fault occurs, it will call the imsic_mmio_write function,the
> guest irq will be written to the guest interrupt file by kvm.

Oh, so the interrupts were "just" slower.  Great job catching that!

>>> ---
>>> diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
>>> @@ -359,8 +360,11 @@ int kvm_riscv_gstage_ioremap(struct kvm *kvm, gpa_t gpa,
>>> +		pte = pte_mkdirty(pte);
>>
>>Is it necessary to dirty the pte?
>>
>>It was dirtied before, so it definitely doesn't hurt,
>
> Make pte dirty is necessary(for hardware without Svadu), and here is
> the first time to make this pte dirty.

Right, we would get a pointless trap otherwise,

Thanks.