[PATCH -next v15 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context

[Conor Dooley]

On Fri, Mar 17, 2023 at 11:35:26AM +0000, Andy Chiu wrote:
> From: Greentime Hu <greentime.hu at sifive.com>
> 
> This patch is used to detect the size of CPU vector registers and use
> riscv_v_vsize to save the size of all the vector registers. It assumes all
> harts has the same capabilities in a SMP system.
> 
> Co-developed-by: Guo Ren <guoren at linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren at linux.alibaba.com>
> Co-developed-by: Vincent Chen <vincent.chen at sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen at sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu at sifive.com>
> Signed-off-by: Andy Chiu <andy.chiu at sifive.com>
> Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

FYI git am complains while applying this patch about whitespace issues:

Applying: riscv: Introduce riscv_v_vsize to record size of Vector context
Using index info to reconstruct a base tree...
M	arch/riscv/kernel/cpufeature.c
.git/rebase-apply/patch:90: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
Falling back to patching base and 3-way merge...

Thanks,
Conor.
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