[V2 PATCH 1/3] x86/panic: Fix re-entrance problem due to panic on NMI

河合英宏 / KAWAI,HIDEHIRO hidehiro.kawai.ez at hitachi.com
Thu Jul 30 01:06:56 PDT 2015


> -----Original Message-----
> From: Michal Hocko [mailto:mhocko at kernel.org]
> On Thu 30-07-15 07:33:15, 河合英宏 / KAWAI,HIDEHIRO wrote:
> [...]
> > Are you using SGI UV?  On that platform, NMIs may be delivered to
> > all cpus because LVT1 of all cpus are not masked as follows:
> This is Compute Blade 520XB1 from Hitachi with 240 cpus.

Thanks for the information!

I asked my colleague in other department about NMI button behavior
of our server just before receive your mail, and certainly what you
said happens; all cpus say "Uhhuh. NMI received for unknown reason 3d
on CPU N" when NMI button is pusshed.  So, this was also our problem...

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