[PATCH] intel-iommu: Synchronize gcmd value with global command register

Takao Indoh indou.takao at jp.fujitsu.com
Mon Apr 15 05:00:13 EDT 2013

(2013/04/10 13:47), Takao Indoh wrote:
> (2013/04/05 20:06), Joerg Roedel wrote:
>> On Wed, Apr 03, 2013 at 09:24:39AM +0100, David Woodhouse wrote:
>>> On Wed, 2013-04-03 at 16:11 +0900, Takao Indoh wrote:
>>>> Yeah, you are right. I forgot such a case.
>>> If you disable translation and there's some device still doing DMA, it's
>>> going to scribble over random areas of memory. You really want to have
>>> translation enabled and all the page tables *cleared*, during kexec. I
>>> think it's fair to insist that the secondary kernel should use the IOMMU
>>> if the first one did.
>> Do we really need to insist on that? The IOMMU initialization on x86
>> happens after the kernel scanned and enumerated the PCI bus. While doing
>> this the kernel (at least it should) disables all devices it finds. So
>> when the IOMMU init code runs we should be safe from any in-flight DMA
>> and can either disable translation or re-initialize it for the kdump
>> kernel. Until then translation needs to stay enabled of course, so that
>> the old page-tables are still used and in-flight DMA doesn't corrupt
>> any data.
> So we should do in this order, right?
> (1) PCI initialization. Stop all ongoing DMA here.
> (2) Disable translation if already enable.
> (3) Make pgtable and enable translation.

Joerg, David,

On DMAR initialization during kdump boot, do you guys agree to change
order like this?

Current order:
(1) Disable translation
(2) PCI initialization
(3) Make pgtable and enable translation.

Order I'm proposing:
(1) PCI initialization
(2) Disable translation
(3) Make pgtable and enable translation.

The purpose to change the behavior is to stop DMA in PCI layer.

As Joerg said, if we need to consider the case that kdump kernel is
compiled without dma-remapping(CONFIG_INTEL_IOMMU is off?), I can update
my patch to handle such a case properly by adding ifdef

About how to stop the DMA on PCI layer, I'll post another mail to
discuss it to iommu and pci list.

Takao Indoh

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