Hi Eric<br><br><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="im">> > <a href="http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c;h=63e87c9551c440edab572f5252a503ba4d533161;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a" target="_blank">http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c;h=63e87c9551c440edab572f5252a503ba4d533161;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a</a><br>
> ><br>
> ><br>
> Now that piece certainly was missing, but how the heck did you find out<br>
> those register values? Where did you get the information about writing to<br>
> chip select 0 and selecting:<br>
><br>
> CSCR0U: 0x00008F03<br>
> CSCR0L: 0xA0330D01<br>
> CSCR0A: 0x002208C0<br>
><br>
</div>you need the reference manual of the i.MX25 to know the meaning of<br>
these registers and the datasheet of your flash to know it's timings<br>
then you can calculate the value to put in the registers.<br><font color="#888888"><br></font></blockquote><div><br></div><div>I have found them in an old uboot tree a previous person patched to have working support for NOR on boot. The values are:</div>
<div><br></div><div><div> { .ptr_type = 4, .addr = 0xB8002000, .val = 0x0000D003, },</div><div> { .ptr_type = 4, .addr = 0xB8002004, .val = 0x00330D01, },</div><div> { .ptr_type = 4, .addr = 0xB8002008, .val = 0x00220800, },</div>
</div><div><br></div><div>Still it does not work at all, it does not display anything upon boot. How could I debug this? I have adapted the DCD header (not needed in my case) according to what the old uboot patches did, I have also put this into my lowlevel_init (which I have studied extensively over the weekend and I start understanding much better):</div>
<div><br></div><div><div>/* Check 24.3.3.1 and 24.5.4.1.1 */</div><div>static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl,</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>uint32_t esdcfg)</div>
<div>{</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>uint32_t esdctlreg = ESDCTL0;</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>uint32_t esdcfgreg = ESDCFG0;</div><div><br>
</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>if (base == 0x90000000) {</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>esdctlreg += 8;</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>esdcfgreg += 8;</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>}</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>esdctl |= ESDCTL0_SDE;</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(esdcfg, esdcfgreg);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(esdctl | ESDCTL0_SMODE_PRECHARGE, esdctlreg);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0, base + 1024);</div><div>
<span class="Apple-tab-span" style="white-space:pre"> </span>writel(esdctl | ESDCTL0_SMODE_AUTO_REFRESH, esdctlreg);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>readb(base);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>readb(base);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(esdctl | ESDCTL0_SMODE_LOAD_MODE, esdctlreg);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writeb(0, base + 0x33);</div><div>
<span class="Apple-tab-span" style="white-space:pre"> </span>writel(esdctl, esdctlreg);</div><div>}</div><div><br></div><div>void __bare_init __naked board_init_lowlevel(void)</div><div>{</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>uint32_t r;</div>
<div>#ifdef CONFIG_NAND_IMX_BOOT</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>unsigned int *trg, *src;</div><div>#endif</div><div><br></div><div> /* restart the MPLL and wait until it's stable */</div>
<div> writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27),</div><div> IMX_CCM_BASE + CCM_CCTL);</div><div> while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {};</div>
<div><br></div><div> /* Configure dividers and ARM clock source</div><div> * ARM @ 400 MHz</div><div> * AHB @ 133 MHz</div><div> */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x20034000, IMX_CCM_BASE + CCM_CCTL);</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* Set up 16bit NOR flash on WEIM CS0 */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xB8002000, 0x0000D003);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xB8002004, 0x00330D01);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xB8002008, 0x00220800);</div><div><br></div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * Set all MPROTx to be non-bufferable, trusted for R/W,</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> * not forced to user-mode.</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x77777777, 0x43f00000);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x77777777, 0x43f00004);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x77777777, 0x53f00000);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x77777777, 0x53f00004);</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* MAX (Multi-Layer AHB Crossbar Switch) setup</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x00043210, 0x43f04000);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x00043210, 0x43f04100);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x00043210, 0x43f04200);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x00043210, 0x43f04300);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x00043210, 0x43f04400);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>/* SGPCR - always park on last master */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x10, 0x43f04010);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x10, 0x43f04110);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x10, 0x43f04210);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x10, 0x43f04310);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x10, 0x43f04410);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>/* MGPCR - restore default values */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x0, 0x43f04800);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x0, 0x43f04900);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x0, 0x43f04a00);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x0, 0x43f04b00);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x0, 0x43f04c00);</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* Configure M3IF registers</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * M3IF Control Register (M3IFCTL) for MX25</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> * MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> * ----------</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * 0x00000001</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x1, 0xb8003000);</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* enable all the clocks */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>/*</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x1fffffff, IMX_CCM_BASE + CCM_CGCR0);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xffffffff, IMX_CCM_BASE + CCM_CGCR1);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x000fdfff, IMX_CCM_BASE + CCM_CGCR2);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>*/</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* Set DDR2 and NFC group driver voltages */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x1000, IMX_IOMUXC_BASE + 0x454);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x2000, IMX_IOMUXC_BASE + 0x448);</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* Skip SDRAM initialization if we run from RAM */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>r = get_pc();</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>if (r > 0x80000000 && r < 0x90000000)</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>board_init_lowlevel_return();</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(ESDMISC_RST, ESDMISC);</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>while (!(readl(ESDMISC) & (1 << 31)));</div>
<div><br></div><div>#define ESDCTLVAL<span class="Apple-tab-span" style="white-space:pre"> </span>(ESDCTL0_ROW13 | ESDCTL0_COL9 |<span class="Apple-tab-span" style="white-space:pre"> </span>ESDCTL0_DSIZ_15_0 | \</div><div>
<span class="Apple-tab-span" style="white-space:pre"> </span> ESDCTL0_REF4 | ESDCTL0_PWDT_PRECHARGE_PWDN | ESDCTL0_BL)</div><div>#define ESDCFGVAL<span class="Apple-tab-span" style="white-space:pre"> </span>(ESDCFGx_tRP_3 | ESDCFGx_tMRD_2 | ESDCFGx_tRAS_6 | \</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 | ESDCFGx_tRCD_3 | \</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> ESDCFGx_tRC_9)</div><div>
<br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL);</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>board_init_lowlevel_return();</div><div>}</div></div><div><br></div><div>Why can't I printf() from low_level?</div><div><br></div><div>
I have also tried to what you did for your eukrea_cpuimx27.c:</div>
<div><br></div><div><div>diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-reg</div><div>index 73307c4..8225832 100644</div><div>--- a/arch/arm/mach-imx/include/mach/imx25-regs.h</div>
<div>+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h</div><div>@@ -72,6 +72,7 @@</div><div> #define CCM_LTR1 0x44</div><div> #define CCM_LTR2 0x48</div><div> #define CCM_LTR3 0x4c</div><div>+#define CCM_MCR 0x64</div>
<div> </div><div> #define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)</div><div> #define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)</div><div>@@ -107,6 +108,22 @@</div><div> #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)</div>
<div> #define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)</div><div> </div><div>+/* Chip Select Registers */</div><div>+#define IMX_WEIM_BASE WEIM_BASE</div><div>+#define CSxU(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x00) /* Chip Select x Upper Register */</div>
<div>+#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip Select x Lower Register */</div><div>+#define CSxA(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x08) /* Chip Select x Addition Register */</div><div>+#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */</div>
<div>+</div><div>+#ifndef __ASSEMBLY__</div><div>+static inline void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional</div><div>+{</div><div>+ CSxU(cs) = upper;</div><div>+ CSxL(cs) = lower;</div>
<div>+ CSxA(cs) = addional;</div><div>+}</div><div>+#endif /* __ASSEMBLY__ */</div><div>+</div><div> /*</div><div> * Definitions for the clocksource driver</div><div> *</div></div><div><br></div><div>No matter what I do, it just does not work.</div>
<div><br></div><div>Regards</div><div>Roberto</div></div>