Hi Sascha<div><br></div><div>Thank you so much for taking your time explaining things the way you did. It certainly cleared things up a lot, albeit it still does not work; comment below.<br><br><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="im">> > I read the different board initialization routines over and over again,<br>
> but can't find a common pattern. From what I see the lowlevel_init (which<br>
> has been converted nicely into a C file), only AIPS, MAX, MPLL core clock,<br>
> all clocks, SDRAM are initialized, but I have seen AIPS and MAX setups in<br>
> core_init functions (eukrea_cpuimx35.c), as well as clock setups in<br>
> console_init and other places. So, what's the bare minimum in lowlevel to<br>
> set up? SDRAM/MDDR? What's the order of things?<br>
><br>
> I am merely asking because I have come a long way trying to debug an issue<br>
> with weird I/O and clock behaviour on the ESDHC and other parts of my mx25<br>
> device.<br>
<br>
</div>- MAX setup is not needed for barebox<br>
- AIPS can most probably be done later aswell<br>
- I'm unsure with the MPLL, that depends on whether the SDRAM clock<br>
depends on it.<br></blockquote><div><br></div><div>In my case I am fairly certain that SDRAM clock does not depend on MPLL. I will be moving MAX and AIPS setup out of lowlevel init, so as to keep it tiny.</div><div> </div>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
You should only setup all dependencies for SDRAM and the SDRAM itself.<br>
Everything else can be done later. What that is for the i.MX25 you<br>
can see in the dcd, here from the Eukrea mx25:<br>
<br>
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {<br>
{ .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, },<br>
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x92100000, },<br>
{ .ptr_type = 1, .addr = 0x80000400, .val = 0x12344321, },<br>
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2100000, },<br>
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },<br>
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },<br>
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2100000, },<br>
{ .ptr_type = 1, .addr = 0x80000033, .val = 0xda, },<br>
{ .ptr_type = 1, .addr = 0x81000000, .val = 0xff, },<br>
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, },<br>
{ .ptr_type = 4, .addr = 0xb8001004, .val = 0x00295729, },<br>
{ .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, },<br>
};<br>
<br>
So basically this means that the SDRAM does not seem to have any<br>
dependencies.<br></blockquote><div><br></div><div>This is the first time I have realized that the DCD actually represents more or less what should be done in the lowlevel init. After carefully reading what you explained and cross-checking with the old uboot, I have come up with the following DCD:</div>
<div><br></div><div><div>struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* NOR flash, CS0_CSCRU, CS0_CSCRL, CS0_CSCRA */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0xB8002000, .val = 0x0000D003, },</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0xB8002004, .val = 0x00330D01, },</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0xB8002008, .val = 0x00220800, },</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>/* DDR2 init */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0xb8001004, .val = 0x0076e83a, }, /* initial value for ESDCFG0 */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000204, }, /* ESD_MISC */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, /* CS0 precharge command */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0x80000f00, .val = 0x12344321, }, /* precharge all dummy write */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, /* Load Mode Register command */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 1, .addr = 0x82000000, .val = 0xda, },<span class="Apple-tab-span" style="white-space:pre"> </span> /* dummy write Load EMR2 */</div><div>
<span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 1, .addr = 0x83000000, .val = 0xda, },<span class="Apple-tab-span" style="white-space:pre"> </span> /* dummy write Load EMR3 */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 1, .addr = 0x81000400, .val = 0xda, },<span class="Apple-tab-span" style="white-space:pre"> </span> /* dummy write Load EMR1; enable DLL */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 1, .addr = 0x80000333, .val = 0xda, },<span class="Apple-tab-span" style="white-space:pre"> </span> /* dummy write Load MR; reset DLL */</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, /* CS0 precharge command */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0x80000400, .val = 0x12345678, }, /* precharge all dummy write */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xA2210000, }, /* select manual refresh mode */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, /* manual refresh */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, /* manual refresh twice */</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, /* Load Mode Register command */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 1, .addr = 0x80000233, .val = 0xda, },<span class="Apple-tab-span" style="white-space:pre"> </span> /* Load MR; CL=3, BL=8, end DLL reset */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 1, .addr = 0x81000780, .val = 0xda, },<span class="Apple-tab-span" style="white-space:pre"> </span> /* Load EMR1; OCD default */</div><div>
<span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 1, .addr = 0x81000400, .val = 0xda, },<span class="Apple-tab-span" style="white-space:pre"> </span> /* Load EMR1; OCD exit */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, }, /* normal mode */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>/* IOMUX_SW_PAD setup */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0x43FAC454, .val = 0x00001000, }, /* IOMUXC_SW_PAD_CTL_GRP_DDRTYPE(1-5) */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0x43FAC448, .val = 0x00002000, }, /* IOMUXC_SW_PAD NFC voltage 1.8 */</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* CLKCTL */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>{ .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, }, /* CLKCTL ARM=399 AHB=133 */</div><div>};</div></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
All the things in lowlevel_init are then done when running from SDRAM<br>
anyway (at least when doing a dcd based boot), so they can safely be<br>
done later.<br>
<br>
The next thing is that the clocks are correctly initialized before the<br>
corresponding devices are registered.<br></blockquote><div><br></div><div>I have seen that some devices simply enable all clocks in lowlevel and some enable the necessary ones at a later stage. To be sure, I have included both versions in my setup, so I can assure that all the necessary clocks are running on boot init.</div>
<div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
So let's analyze Eukreas lowlevel init:<br>
<br>
<br>
> void __bare_init __naked board_init_lowlevel(void)<br>
> {<br>
> uint32_t r;<br>
> #ifdef CONFIG_NAND_IMX_BOOT<br>
> unsigned int *trg, *src;<br>
> int i;<br>
> #endif<br>
> register uint32_t loops = 0x20000;<br>
><br>
> /* restart the MPLL and wait until it's stable */<br>
> writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27),<br>
> IMX_CCM_BASE + CCM_CCTL);<br>
> while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {};<br>
><br>
> /* Configure dividers and ARM clock source<br>
> * ARM @ 400 MHz<br>
> * AHB @ 133 MHz<br>
> */<br>
> writel(0x20034000, IMX_CCM_BASE + CCM_CCTL);<br>
<br>
This may influence the timer clock, so it can be here.<br></blockquote><div><br></div><div>I have copied this, since it was also done in the old uboot version that works.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
><br>
> /* Enable UART1 / FEC / */<br>
> /* writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0);<br>
> writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1);<br>
> writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2);*/<br>
<br>
This brings the Clock gate registers to reset default. This may be a<br>
good idea, but can be done later.<br></blockquote><div><br></div><div>Ok, I have copied this. </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
><br>
> /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.<br>
> * Set all MPROTx to be non-bufferable, trusted for R/W,<br>
> * not forced to user-mode.<br>
> */<br>
> writel(0x77777777, 0x43f00000);<br>
> writel(0x77777777, 0x43f00004);<br>
> writel(0x77777777, 0x53f00000);<br>
> writel(0x77777777, 0x53f00004);<br>
<br>
This can be done later. This is duplicated in many boards and is always<br>
the same. Look for example at the i.MX53 code, there we have<br>
imx53_init_lowlevel() which sets up the AIPS. This is common for all<br>
i.MX53 and is called from an initcall. Similar could be done for i.MX25<br>
aswell, if somebody is willing to implement it.<br></blockquote><div><br></div><div>I like the imx53_init_lowlevel() approach a lot, it's very clean and helps avoiding redundancy and maintenance costs. If I get my device to boot from NOR, I might be inclined to give it a shot.</div>
<div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
><br>
> /* MAX (Multi-Layer AHB Crossbar Switch) setup<br>
> * MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB<br>
> */<br>
> writel(0x00002143, 0x43f04000);<br>
> writel(0x00002143, 0x43f04100);<br>
> writel(0x00002143, 0x43f04200);<br>
> writel(0x00002143, 0x43f04300);<br>
> writel(0x00002143, 0x43f04400);<br>
> /* SGPCR - always park on last master */<br>
> writel(0x10, 0x43f04010);<br>
> writel(0x10, 0x43f04110);<br>
> writel(0x10, 0x43f04210);<br>
> writel(0x10, 0x43f04310);<br>
> writel(0x10, 0x43f04410);<br>
> /* MGPCR - restore default values */<br>
> writel(0x0, 0x43f04800);<br>
> writel(0x0, 0x43f04900);<br>
> writel(0x0, 0x43f04a00);<br>
> writel(0x0, 0x43f04b00);<br>
> writel(0x0, 0x43f04c00);<br>
><br>
> /* Configure M3IF registers<br>
> * M3IF Control Register (M3IFCTL) for MX25<br>
> * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001<br>
> * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000<br>
> * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000<br>
> * MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000<br>
> * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000<br>
> * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000<br>
> * MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000<br>
> * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000<br>
> * ----------<br>
> * 0x00000001<br>
> */<br>
> writel(0x1, 0xb8003000);<br>
<br>
Same as above.<br>
<br>
><br>
> /* Speed up NAND controller by adjusting the NFC divider */<br>
> r = readl(IMX_CCM_BASE + CCM_PCDR2);<br>
> r &= ~0xf;<br>
> r |= 0x1;<br>
> writel(r, IMX_CCM_BASE + CCM_PCDR2);<br>
<br>
This is necessary for external NAND boot. The NAND controller comes up<br>
with a low speed which makes the copying of the image<br>
(CONFIG_NAND_IMX_BOOT below) slow. This is optional but has to be done<br>
here to get a faster boot.<br>
<br></blockquote><div>Ok, I reckon there is nothing comparable which should be done in the NOR case.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
><br>
> /* Skip SDRAM initialization if we run from RAM */<br>
> r = get_pc();<br>
> if (r > 0x80000000 && r < 0x90000000)<br>
> board_init_lowlevel_return();<br>
<br>
Here we bail out for second stage boots (and also internal bootmode<br>
where we are already running from SDRAM<br></blockquote><div><br></div><div>It's this place where I wanted to put a printf() to see where the code is actually branching and if my setting of the corresponding WEIM CS0 registers upset the processor already. However, it seems as if printf()'s here is a no-go. </div>
<div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
><br>
> /* Init Mobile DDR */<br>
> writel(0x0000000E, ESDMISC);<br>
> writel(0x00000004, ESDMISC);<br>
> __asm__ volatile ("1:\n"<br>
> "subs %0, %1, #1\n"<br>
> "bne 1b":"=r" (loops):"0" (loops));<br>
><br>
> writel(0x0029572B, ESDCFG0);<br>
> writel(0x92210000, ESDCTL0);<br>
> writeb(0xda, IMX_SDRAM_CS0 + 0x400);<br>
> writel(0xA2210000, ESDCTL0);<br>
> writeb(0xda, IMX_SDRAM_CS0);<br>
> writeb(0xda, IMX_SDRAM_CS0);<br>
> writel(0xB2210000, ESDCTL0);<br>
> writeb(0xda, IMX_SDRAM_CS0 + 0x33);<br>
> writeb(0xda, IMX_SDRAM_CS0 + 0x1000000);<br>
> writel(0x82216080, ESDCTL0);<br>
<br>
RAM init for external bootmode, has to be done here.<br></blockquote><div><br></div><div>I left it there.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
><br>
> #ifdef CONFIG_NAND_IMX_BOOT<br>
> /* skip NAND boot if not running from NFC space */<br>
> r = get_pc();<br>
> if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)<br>
> board_init_lowlevel_return();<br>
><br>
> src = (unsigned int *)IMX_NFC_BASE;<br>
> trg = (unsigned int *)TEXT_BASE;<br>
><br>
> /* Move ourselves out of NFC SRAM */<br>
> for (i = 0; i < 0x800 / sizeof(int); i++)<br>
> *trg++ = *src++;<br>
><br>
> /* Jump to SDRAM */<br>
> r = (unsigned int)&insdram;<br>
> __asm__ __volatile__("mov pc, %0" : : "r"(r));<br>
> #else<br>
> board_init_lowlevel_return();<br>
> #endif<br>
<br>
Finally copy the image from NAND SRAM to SDRAM, only needed for external<br>
NAND boot.<br>
<br></blockquote><div>And since I am trying to perform an internal MMC or NOR boot, this does not affect me at all.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Often the whole lowlevel stuff is setup in early assembly code. This has<br>
mostly historical reasons and 'hey, this is hardcore stuff we configure<br>
here, we must do it early and we must do it in assembly'. Much of the<br>
lowlevel stuff we have in barebox is just copied from a working U-Boot<br>
or redboot setup and never touched again, hence the slightly chaotic<br>
situation.<br></blockquote><div><br></div><div>This is what I have slowly come to understand while reading more source code over the weekend. I have also found the old uboot init part for this device from 2009.08 and have adapted my lowlevel and device part code accordingly. I wonder if someone could write a quick and dirty perl/shell script to auto-port devices from uboot to barebox, at least the basic booting facility.</div>
<div><br></div><div>In my case, there is one peculiarity in the u-boot sources, which I haven't been able to map to barebox yet and it's best described by the corresponding code:</div><div><br></div><div><div>#include <common.h></div>
<div>#include <asm/io.h></div><div>#include <asm/errno.h></div><div>#include <asm/arch/mx25.h></div><div>#include <asm/arch/mx25-regs.h></div><div>#include <asm/arch/mx25_pins.h></div><div>#include <asm/arch/iomux.h></div>
<div>#include <asm/arch/gpio.h></div><div>#include <imx_spi.h></div><div><br></div><div>#ifdef CONFIG_CMD_MMC</div><div>#include <mmc.h></div><div>#include <fsl_esdhc.h></div><div>#endif</div><div>
<br></div><div>DECLARE_GLOBAL_DATA_PTR;</div><div><br></div><div>static u32 system_rev;</div><div><br></div><div>u32 get_board_rev(void)</div><div>{</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>return system_rev;</div>
<div>}</div><div><br></div><div>static inline void setup_soc_rev(void)</div><div>{</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>int reg;</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>reg = __REG(IIM_BASE + IIM_SREV);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>if (!reg) {</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>reg = __REG(ROMPATCH_REV);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>reg <<= 4;</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>} else</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>reg += CHIP_REV_1_0;</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>system_rev = 0x25000 + (reg & 0xFF);</div>
<div>}</div><div><br></div><div>inline int is_soc_rev(int rev)</div><div>{</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>return (system_rev & 0xFF) - rev;</div><div>}</div><div><br></div><div>
int dram_init(void)</div><div>{</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>gd->bd->bi_dram[0].start = PHYS_SDRAM_1;</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>return 0;</div><div>}</div><div><br></div><div>#ifdef CONFIG_CMD_MMC</div><div><br></div><div>u32 *imx_esdhc_base_addr;</div><div><br></div>
<div>int esdhc_gpio_init(void)</div><div>{</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>u32 interface_esdhc = 0, val = 0;</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>interface_esdhc = (readl(CCM_RCSR) & (0x00300000)) >> 20;</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>switch (interface_esdhc) {</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>case 0:</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>imx_esdhc_base_addr = (u32 *)MMC_SDHC1_BASE;</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>/* Pins */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x10, IOMUXC_BASE + 0x190);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SD1_CMD */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x10, IOMUXC_BASE + 0x194);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SD1_CLK */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x00, IOMUXC_BASE + 0x198);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SD1_DATA0 */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x00, IOMUXC_BASE + 0x19c);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SD1_DATA1 */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x00, IOMUXC_BASE + 0x1a0);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SD1_DATA2 */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x00, IOMUXC_BASE + 0x1a4);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SD1_DATA3 */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/*ENABLE NOR</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x06, IOMUXC_BASE + 0x094);<span class="Apple-tab-span" style="white-space:pre"> </span>// D12 (SD1_DATA4)</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x06, IOMUXC_BASE + 0x090);<span class="Apple-tab-span" style="white-space:pre"> </span>// D13 (SD1_DATA5)</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x06, IOMUXC_BASE + 0x08c);<span class="Apple-tab-span" style="white-space:pre"> </span>// D14 (SD1_DATA6)</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x06, IOMUXC_BASE + 0x088);<span class="Apple-tab-span" style="white-space:pre"> </span>// D15 (SD1_DATA7)</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x05, IOMUXC_BASE + 0x010);<span class="Apple-tab-span" style="white-space:pre"> </span>// A14 (SD1_WP)</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x05, IOMUXC_BASE + 0x014);<span class="Apple-tab-span" style="white-space:pre"> </span>// A15 (SD1_DET)</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>*/</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* Pads */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x388);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SD1_CMD */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x38c);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SD1_CLK */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x390);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SD1_DATA0 */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x394);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SD1_DATA1 */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x398);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SD1_DATA2 */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x39c);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SD1_DATA3 */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* ENABLE NOR</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x28c);<span class="Apple-tab-span" style="white-space:pre"> </span>// D12 (SD1_DATA4)</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x288);<span class="Apple-tab-span" style="white-space:pre"> </span>// D13 (SD1_DATA5)</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x284);<span class="Apple-tab-span" style="white-space:pre"> </span>// D14 (SD1_DATA6)</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x280);<span class="Apple-tab-span" style="white-space:pre"> </span>// D15 (SD1_DATA7)</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x230);<span class="Apple-tab-span" style="white-space:pre"> </span>// A14 (SD1_WP)</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x234);<span class="Apple-tab-span" style="white-space:pre"> </span>// A15 (SD1_DET)</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>*/</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/*</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * Set write protect and card detect gpio as inputs</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> * A14 (SD1_WP) and A15 (SD1_DET)</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>val = ~(3 << 0) & readl(GPIO1_BASE + GPIO_GDIR);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(val, GPIO1_BASE + GPIO_GDIR);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>break;</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>case 1:</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>imx_esdhc_base_addr = (u32 *)MMC_SDHC2_BASE;</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* Pins */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x16, IOMUXC_BASE + 0x0e8);<span class="Apple-tab-span" style="white-space:pre"> </span>/* LD8 (SD1_CMD) */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x16, IOMUXC_BASE + 0x0ec);<span class="Apple-tab-span" style="white-space:pre"> </span>/* LD9 (SD1_CLK) */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x06, IOMUXC_BASE + 0x0f0);<span class="Apple-tab-span" style="white-space:pre"> </span>/* LD10 (SD1_DATA0) */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x06, IOMUXC_BASE + 0x0f4);<span class="Apple-tab-span" style="white-space:pre"> </span>/* LD11 (SD1_DATA1) */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x06, IOMUXC_BASE + 0x0f8);<span class="Apple-tab-span" style="white-space:pre"> </span>/* LD12 (SD1_DATA2) */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x06, IOMUXC_BASE + 0x0fc);<span class="Apple-tab-span" style="white-space:pre"> </span>/* LD13 (SD1_DATA3) */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x02, IOMUXC_BASE + 0x120);<span class="Apple-tab-span" style="white-space:pre"> </span>/* CSI_D2 (SD1_DATA4) */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x02, IOMUXC_BASE + 0x124);<span class="Apple-tab-span" style="white-space:pre"> </span>/* CSI_D3 (SD1_DATA5) */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x02, IOMUXC_BASE + 0x128);<span class="Apple-tab-span" style="white-space:pre"> </span>/* CSI_D4 (SD1_DATA6) */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x02, IOMUXC_BASE + 0x12c);<span class="Apple-tab-span" style="white-space:pre"> </span>/* CSI_D5 (SD1_DATA7) */</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* Pads */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x2e0);<span class="Apple-tab-span" style="white-space:pre"> </span>/* LD8 (SD1_CMD) */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x2e4);<span class="Apple-tab-span" style="white-space:pre"> </span>/* LD9 (SD1_CLK) */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x2e8);<span class="Apple-tab-span" style="white-space:pre"> </span>/* LD10 (SD1_DATA0) */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x2ec);<span class="Apple-tab-span" style="white-space:pre"> </span>/* LD11 (SD1_DATA1) */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x2f0);<span class="Apple-tab-span" style="white-space:pre"> </span>/* LD12 (SD1_DATA2) */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x2f4);<span class="Apple-tab-span" style="white-space:pre"> </span>/* LD13 (SD1_DATA3) */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x318);<span class="Apple-tab-span" style="white-space:pre"> </span>/* CSI_D2 (SD1_DATA4) */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x31c);<span class="Apple-tab-span" style="white-space:pre"> </span>/* CSI_D3 (SD1_DATA5) */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x320);<span class="Apple-tab-span" style="white-space:pre"> </span>/* CSI_D4 (SD1_DATA6) */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0xD1, IOMUXC_BASE + 0x324);<span class="Apple-tab-span" style="white-space:pre"> </span>/* CSI_D5 (SD1_DATA7) */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>break;</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>default:</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>break;</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>}</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>return 0;</div><div>}</div><div><br></div><div>int board_mmc_init(void)</div><div>
{</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>if (!esdhc_gpio_init())</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>return fsl_esdhc_mmc_init(gd->bd);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>else</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>return -1;</div><div>}</div><div>#endif</div><div><br></div><div>void spi_io_init(struct imx_spi_dev_t *dev)</div><div>{</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>switch (dev->base) {</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>case CSPI1_BASE:</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0, IOMUXC_BASE + 0x180);<span class="Apple-tab-span" style="white-space:pre"> </span>/* CSPI1 SCLK */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x1C0, IOMUXC_BASE + 0x5c4);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0, IOMUXC_BASE + 0x184);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SPI_RDY */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x1E0, IOMUXC_BASE + 0x5c8);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0, IOMUXC_BASE + 0x170);<span class="Apple-tab-span" style="white-space:pre"> </span>/* MOSI */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x1C0, IOMUXC_BASE + 0x5b4);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0, IOMUXC_BASE + 0x174);<span class="Apple-tab-span" style="white-space:pre"> </span>/* MISO */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x1C0, IOMUXC_BASE + 0x5b8);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0, IOMUXC_BASE + 0x17C);<span class="Apple-tab-span" style="white-space:pre"> </span>/* SS1 */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x1E0, IOMUXC_BASE + 0x5C0);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>break;</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>default:</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>break;</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>}</div><div>}</div><div><br></div><div>int board_init(void)</div><div>{</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>setup_soc_rev();</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* setup pins for UART1 */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* UART 1 IOMUX Configs */</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_UART1_RXD, MUX_CONFIG_FUNC);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_UART1_TXD, MUX_CONFIG_FUNC);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_FUNC);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_UART1_CTS, MUX_CONFIG_FUNC);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_UART1_RXD,</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_UART1_TXD,</div><div>
<span class="Apple-tab-span" style="white-space:pre"> </span>PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_UART1_RTS,</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_UART1_CTS,</div><div>
<span class="Apple-tab-span" style="white-space:pre"> </span>PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* setup pins for FEC */</div><div>
<span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_FEC_MDC, MUX_CONFIG_FUNC);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_FEC_MDIO, MUX_CONFIG_FUNC);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_POWER_FAIL, MUX_CONFIG_FUNC); /* PHY INT */</div><div><br></div><div>#define FEC_PAD_CTL1 (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PUE_PUD | \</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>PAD_CTL_PKE_ENABLE)</div><div>#define FEC_PAD_CTL2 (PAD_CTL_PUE_PUD)</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_FEC_TX_CLK, FEC_PAD_CTL1);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_FEC_RX_DV, FEC_PAD_CTL1);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_FEC_RDATA0, FEC_PAD_CTL1);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_FEC_TDATA0, FEC_PAD_CTL2);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_FEC_TX_EN, FEC_PAD_CTL2);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_FEC_MDC, FEC_PAD_CTL2);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_FEC_MDIO, FEC_PAD_CTL1 | PAD_CTL_22K_PU);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_FEC_RDATA1, FEC_PAD_CTL1);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_FEC_TDATA1, FEC_PAD_CTL2);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_POWER_FAIL, FEC_PAD_CTL1);</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/*</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> * Assert FEC_RESET_B, then power up the PHY by asserting</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * FEC_ENABLE, at the same time lifting FEC_RESET_B.</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> *</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin D12</div><div><span class="Apple-tab-span" style="white-space:pre"> </span> * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin A17</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span> */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/*FQ FOR ENABLE NOR</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_A17, MUX_CONFIG_ALT5); // FEC_EN</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_D12, MUX_CONFIG_ALT5); // FEC_RESET_B</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_A17, PAD_CTL_ODE_OpenDrain);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_D12, 0);</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_set_gpio_direction(MX25_PIN_A17, 0); // FEC_EN</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_set_gpio_direction(MX25_PIN_D12, 0); // FEC_RESET_B</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* drop PHY power</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_set_gpio_dataout(MX25_PIN_A17, 0);<span class="Apple-tab-span" style="white-space:pre"> </span>// FEC_EN</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>// assert reset</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_set_gpio_dataout(MX25_PIN_D12, 0);<span class="Apple-tab-span" style="white-space:pre"> </span>// FEC_RESET_B</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>udelay(2);<span class="Apple-tab-span" style="white-space:pre"> </span>// spec says 1us min</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>// turn on PHY power and lift reset</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_set_gpio_dataout(MX25_PIN_A17, 1);<span class="Apple-tab-span" style="white-space:pre"> </span>// FEC_EN</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_set_gpio_dataout(MX25_PIN_D12, 1);<span class="Apple-tab-span" style="white-space:pre"> </span>// FEC_RESET_B</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>*/</div>
<div><br></div><div>#define I2C_PAD_CTL (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | \</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_ODE_OpenDrain)</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_I2C1_CLK, MUX_CONFIG_SION);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_request_iomux(MX25_PIN_I2C1_DAT, MUX_CONFIG_SION);</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_I2C1_CLK, 0x1E8);</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_iomux_set_pad(MX25_PIN_I2C1_DAT, 0x1E8);</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>gd->bd->bi_arch_number = MACH_TYPE_MX25_3DS; /* board id for linux */</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>gd->bd->bi_boot_params = 0x80000100; /* address of boot parameters */</div>
<div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>return 0;</div><div><br></div><div>#undef FEC_PAD_CTL1</div><div>#undef FEC_PAD_CTL2</div><div>#undef I2C_PAD_CTL</div><div>}</div><div><br>
</div><div>#ifdef BOARD_LATE_INIT</div><div>int board_late_init(void)</div><div>{</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>u8 reg[4];</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>/* Turn PMIC On*/</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>reg[0] = 0x09;</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>i2c_write(0x54, 0x02, 1, reg, 1);</div><div><br></div><div>#ifdef CONFIG_IMX_SPI_CPLD</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>mxc_cpld_spi_init();</div><div>#endif</div><div><br></div><div><span class="Apple-tab-span" style="white-space:pre"> </span>return 0;</div><div>}</div><div>
#endif</div><div><br></div><div><br></div><div>int checkboard(void)</div><div>{</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>printf("Boot Device: SD Card \n");</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>printf("Board: SID1 i.MX25 \n");</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>return 0;</div><div>}</div><div><br></div><div>int board_eth_init(bd_t *bis)</div><div>{</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>int rc = -ENODEV;</div>
<div>#if defined(CONFIG_SMC911X)</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);</div><div>#endif</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>return rc;</div>
<div>}</div></div><div> </div><div>It seems as if in order to support NOR upon boot, the following PADs and PINs have to be disabled:</div><div><br></div><div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x06, IOMUXC_BASE + 0x094);<span class="Apple-tab-span" style="white-space:pre"> </span>// D12 (SD1_DATA4)</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x06, IOMUXC_BASE + 0x090);<span class="Apple-tab-span" style="white-space:pre"> </span>// D13 (SD1_DATA5)</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x06, IOMUXC_BASE + 0x08c);<span class="Apple-tab-span" style="white-space:pre"> </span>// D14 (SD1_DATA6)</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x06, IOMUXC_BASE + 0x088);<span class="Apple-tab-span" style="white-space:pre"> </span>// D15 (SD1_DATA7)</div><div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x05, IOMUXC_BASE + 0x010);<span class="Apple-tab-span" style="white-space:pre"> </span>// A14 (SD1_WP)</div>
<div><span class="Apple-tab-span" style="white-space:pre"> </span>writel(0x05, IOMUXC_BASE + 0x014);<span class="Apple-tab-span" style="white-space:pre"> </span>// A15 (SD1_DET)</div></div><div><br></div><div>Why, and how could I find the corresponding barebox mappings? I recall that last week someone wanted to synchronize the IOMUX settings with the kernel ones. But still, why this change and could this affect my issue I am seeing with barebox? I still cannot initialize the NOR upon MMC internal boot on my device.</div>
<div><br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hope I could help you a bit.<br>
<div class="HOEnZb"><div class="h5"><br></div></div></blockquote><div><br></div><div>A lot, let me know where I can send the beers or any beverage to as soon as I get the bloody thing booting from NOR and showing up my NOR :).</div>
<div><br></div><div>Take care</div><div>Roberto </div></div></div>