Hi Eric<br><br><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="im">> > well NAND boot + nand rootfs works fine here (cpuimx25) and I assume<br>
> > NAND boot + sd rootfs would work as sd is properly detected during boot.<br>
> ><br>
> > Yep, I believe it's more a question of me setting the parameters correctly<br>
> upon boot. But without a proper low level init (which I don't have because<br>
> I do not really understand all the details of the low level code), there<br>
> are other factors which could inhibit the proper boot, as you mention below.<br>
><br>
</div>if your sd's partitions are detected by the kernel you must be able to<br>
boot a rootfs on it it's just a bootargs problem (and kernel<br>
configuration to have the right FS included).<br></blockquote><div><br></div><div>That's my understanding too, however it does not work at the moment. But what's really important is that I have NOR support when loading barebox as first stage boot loader from SD card.</div>
<div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="im">> I suppose WEIM configuration is done in the low level part, isn't it? Where<br>
> would I find an appropriate example? I have been reading all the fsl<br>
> board's low_level codes, but have a hard time figuring out how to apply it<br>
> to my board.<br>
><br>
> With regard to the IOMUX, I was under the impression that it does not<br>
> matter much, since after low level code run, the execution path is:<br>
><br>
> late_initcall()<br>
> mem_initcall()<br>
> device_initcall() --> add_cfi_flash_device()<br>
> console_initcall() --> mxc_iomux_v3_setup_multiple_pads()<br>
> core_initcall()<br>
><br>
> So CFI/NOR detection happens before IOMUX setup, at least that's what I<br>
> have gathered for my board copying from various other examples in barebox.<br>
> What would the correct code execution path be from the architectural point<br>
> of view?<br>
><br>
</div>nothing prevents you from moving mxc_iomux_v3_setup_multiple_pads to<br>
device_initcall as done in<br>
<a href="http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c;h=1b8f618138023b88893a024ddc0c078b7b9f2325;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a" target="_blank">http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c;h=1b8f618138023b88893a024ddc0c078b7b9f2325;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a</a><br>
<br></blockquote><div>Thanks, I have done this now, looks much cleaner. Stil, I wonder about the order of things when powering and booting up the mx25 in general.</div><div><br></div><div> lowlevel -> AIPS -> MAX (MPR, SGPCR, MGPCR) -> M3IF -> MPLL clock -> other clocks</div>
<div><div> late_initcall -> fec_init</div><div> mem_initcall -> imx25_mem_init</div><div> device_initcall -> devices_init</div><div> console_initcall -> console_init</div><div> core_initcall -> core_setup</div>
</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
for the weim setting you may need to do something similar to what is<br>
done on line 187 of :<br>
<a href="http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c;h=63e87c9551c440edab572f5252a503ba4d533161;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a" target="_blank">http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c;h=63e87c9551c440edab572f5252a503ba4d533161;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a</a><br>
<font color="#888888"><br></font></blockquote><div><br></div><div>Now that piece certainly was missing, but how the heck did you find out those register values? Where did you get the information about writing to chip select 0 and selecting:</div>
<div><br></div><div>CSCR0U: 0x00008F03</div><div>CSCR0L: 0xA0330D01</div><div>CSCR0A: 0x002208C0</div><div><br></div><div>I have patched mx25-regs.h accordingly and added an equivalent call using the same register values:</div>
<div><br></div><div>diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h</div><div>index 73307c4..8225832 100644</div><div>--- a/arch/arm/mach-imx/include/mach/imx25-regs.h</div>
<div>+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h</div><div>@@ -72,6 +72,7 @@</div><div> #define CCM_LTR1<span class="Apple-tab-span" style="white-space:pre"> </span>0x44</div><div> #define CCM_LTR2<span class="Apple-tab-span" style="white-space:pre"> </span>0x48</div>
<div> #define CCM_LTR3<span class="Apple-tab-span" style="white-space:pre"> </span>0x4c</div><div>+#define CCM_MCR<span class="Apple-tab-span" style="white-space:pre"> </span>0x64</div><div> </div><div> #define PDR0_AUTO_MUX_DIV(x)<span class="Apple-tab-span" style="white-space:pre"> </span>(((x) & 0x7) << 9)</div>
<div> #define PDR0_CCM_PER_AHB(x)<span class="Apple-tab-span" style="white-space:pre"> </span>(((x) & 0x7) << 12)</div><div>@@ -107,6 +108,22 @@</div><div> #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)</div>
<div> #define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)</div><div> </div><div>+/* Chip Select Registers */</div><div>+#define IMX_WEIM_BASE WEIM_BASE</div><div>+#define CSxU(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x00) /* Chip Select x Upper Register */</div>
<div>+#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip Select x Lower Register */</div><div>+#define CSxA(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x08) /* Chip Select x Addition Register */</div><div>+#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */</div>
<div>+</div><div>+#ifndef __ASSEMBLY__</div><div>+static inline void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional)</div><div>+{</div><div>+ CSxU(cs) = upper;</div><div>+ CSxL(cs) = lower;</div>
<div>+ CSxA(cs) = addional;</div><div>+}</div><div>+#endif /* __ASSEMBLY__ */</div><div>+</div><div> /*</div><div> * Definitions for the clocksource driver</div><div> *</div><div><br></div><div>But it still does not work. What could be missing? How can I find out more about which chip select I need? I'm practically married to the MX25-RM documentation, but still, it's one heck of a large piece of documentation. I found the following example (using cs2), but I am not sure this helps:</div>
<div><br></div>
<p class="p1">@; config WEIM to Async access with EDC, OEA, RWA, RWN, EBC, 16 bit port and PSR WRITE WEIM_CSCR2U, 0x12020802</p>
<p class="p1">WRITE WEIM_CSCR2L, 0x80330d03</p>
<p class="p1">@ ; config Flash to WRAP 8 mode (by half word accesses) WRITE_H (CS2_BASE_ADDR+0x2384), 0x60<span class="Apple-tab-span"> </span>@ ; offset = 0x11c2 << 1 for 16 bit port WRITE_H (CS2_BASE_ADDR+0x2384), 0x03</p>
<p class="p1">WRITE_H (CS2_BASE_ADDR+0x0), 0xff<span class="Apple-tab-span"> </span>@ ; Flash to read mode</p>
<p class="p1">@ ; config to WEIM Sync access with WRAP8, 16 bit port WRITE WEIM_CSCR2U, 0x13510802</p>
<div>WRITE WEIM_CSCR2L, 0x80330d03</div><div><br></div><div>Could it be that I am missing an iomux setting? Clock missing? I am fairly certain that my NOR is at CS0, so the above example from the RM does not help much, I suppose.</div>
<div><br></div><div>Best regards</div><div>Roberto </div></div>