<br><br><div class="gmail_quote">2011/12/20 <span dir="ltr"><<a href="mailto:franck.jullien@gmail.com">franck.jullien@gmail.com</a>></span><br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
From: Franck Jullien <<a href="mailto:franck.jullien@gmail.com">franck.jullien@gmail.com</a>><br>
<br>
OpenRISC is the original flagship project of the OpenCores community.<br>
This project aims to develop a series of general purpose open source<br>
RISC CPU architectures.<br>
<br>
A team from OpenCores provided the first implementation, the OpenRISC<br>
1200, written in the Verilog hardware description language.<br>
<br>
Even though I should have created an mach-or1200 directory, it is not<br>
necessary for now. The OpenRISC 1200 CPU is the only one available and<br>
it will be for some time.<br>
<br>
Signed-off-by: Franck Jullien <<a href="mailto:franck.jullien@gmail.com">franck.jullien@gmail.com</a>><br>
---<br>
arch/openrisc/Kconfig | 29 ++<br>
arch/openrisc/Makefile | 21 ++<br>
arch/openrisc/configs/generic_defconfig | 20 +<br>
arch/openrisc/cpu/Makefile | 5 +<br>
arch/openrisc/cpu/barebox.lds.S | 98 +++++<br>
arch/openrisc/cpu/cache.c | 154 ++++++++<br>
arch/openrisc/cpu/cpu.c | 43 +++<br>
arch/openrisc/cpu/exceptions.c | 84 +++++<br>
arch/openrisc/cpu/start.S | 335 ++++++++++++++++++<br>
arch/openrisc/include/asm/barebox.h | 4 +<br>
arch/openrisc/include/asm/bitops.h | 28 ++<br>
arch/openrisc/include/asm/bitops/ffs.h | 26 ++<br>
arch/openrisc/include/asm/bitops/fls.h | 26 ++<br>
arch/openrisc/include/asm/byteorder.h | 1 +<br>
arch/openrisc/include/asm/cache.h | 47 +++<br>
arch/openrisc/include/asm/common.h | 4 +<br>
arch/openrisc/include/asm/elf.h | 107 ++++++<br>
arch/openrisc/include/asm/io.h | 123 +++++++<br>
arch/openrisc/include/asm/openrisc_exc.h | 41 +++<br>
arch/openrisc/include/asm/posix_types.h | 71 ++++<br>
arch/openrisc/include/asm/ptrace.h | 131 +++++++<br>
arch/openrisc/include/asm/sections.h | 1 +<br>
arch/openrisc/include/asm/spr-defs.h | 567 ++++++++++++++++++++++++++++++<br>
arch/openrisc/include/asm/string.h | 4 +<br>
arch/openrisc/include/asm/swab.h | 4 +<br>
arch/openrisc/include/asm/system.h | 39 ++<br>
arch/openrisc/include/asm/types.h | 79 ++++<br>
arch/openrisc/lib/Makefile | 6 +<br>
arch/openrisc/lib/ashldi3.S | 41 +++<br>
arch/openrisc/lib/board.c | 42 +++<br>
arch/openrisc/lib/clock.c | 50 +++<br>
arch/openrisc/lib/cpuinfo.c | 156 ++++++++<br>
arch/openrisc/lib/lshrdi3.S | 41 +++<br>
arch/openrisc/lib/muldi3.S | 58 +++<br>
34 files changed, 2486 insertions(+), 0 deletions(-)<br>
create mode 100644 arch/openrisc/Kconfig<br>
create mode 100644 arch/openrisc/Makefile<br>
create mode 100644 arch/openrisc/configs/generic_defconfig<br>
create mode 100644 arch/openrisc/cpu/Makefile<br>
create mode 100644 arch/openrisc/cpu/barebox.lds.S<br>
create mode 100644 arch/openrisc/cpu/cache.c<br>
create mode 100644 arch/openrisc/cpu/cpu.c<br>
create mode 100644 arch/openrisc/cpu/exceptions.c<br>
create mode 100644 arch/openrisc/cpu/start.S<br>
create mode 100644 arch/openrisc/include/asm/barebox.h<br>
create mode 100644 arch/openrisc/include/asm/bitops.h<br>
create mode 100644 arch/openrisc/include/asm/bitops/ffs.h<br>
create mode 100644 arch/openrisc/include/asm/bitops/fls.h<br>
create mode 100644 arch/openrisc/include/asm/byteorder.h<br>
create mode 100644 arch/openrisc/include/asm/cache.h<br>
create mode 100644 arch/openrisc/include/asm/common.h<br>
create mode 100644 arch/openrisc/include/asm/elf.h<br>
create mode 100644 arch/openrisc/include/asm/io.h<br>
create mode 100644 arch/openrisc/include/asm/openrisc_exc.h<br>
create mode 100644 arch/openrisc/include/asm/posix_types.h<br>
create mode 100644 arch/openrisc/include/asm/ptrace.h<br>
create mode 100644 arch/openrisc/include/asm/sections.h<br>
create mode 100644 arch/openrisc/include/asm/spr-defs.h<br>
create mode 100644 arch/openrisc/include/asm/string.h<br>
create mode 100644 arch/openrisc/include/asm/swab.h<br>
create mode 100644 arch/openrisc/include/asm/system.h<br>
create mode 100644 arch/openrisc/include/asm/types.h<br>
create mode 100644 arch/openrisc/lib/Makefile<br>
create mode 100644 arch/openrisc/lib/ashldi3.S<br>
create mode 100644 arch/openrisc/lib/board.c<br>
create mode 100644 arch/openrisc/lib/clock.c<br>
create mode 100644 arch/openrisc/lib/cpuinfo.c<br>
create mode 100644 arch/openrisc/lib/lshrdi3.S<br>
create mode 100644 arch/openrisc/lib/muldi3.S<br>
<br>
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig<br>
new file mode 100644<br>
index 0000000..a3cb337<br>
--- /dev/null<br>
+++ b/arch/openrisc/Kconfig<br>
@@ -0,0 +1,29 @@<br>
+config OPENRISC<br>
+ bool<br>
+ select HAVE_CONFIGURABLE_MEMORY_LAYOUT<br>
+ default y<br>
+<br>
+# not used<br>
+config ARCH_TEXT_BASE<br>
+ hex<br>
+ default 0x00000000<br>
+<br>
+config BOARDINFO<br>
+ default "Openrisc simulator" if GENERIC<br>
+<br>
+choice<br>
+ prompt "Select your board"<br>
+<br>
+config GENERIC<br>
+ bool "Generic "<br>
+ select OPENRISC<br>
+<br>
+endchoice<br>
+<br>
+source common/Kconfig<br>
+source commands/Kconfig<br>
+source net/Kconfig<br>
+source drivers/Kconfig<br>
+source fs/Kconfig<br>
+source lib/Kconfig<br>
+source crypto/Kconfig<br>
diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile<br>
new file mode 100644<br>
index 0000000..fd8bbbf<br>
--- /dev/null<br>
+++ b/arch/openrisc/Makefile<br>
@@ -0,0 +1,21 @@<br>
+CPPFLAGS += -D__OR1K__ -ffixed-r10 -mhard-mul -mhard-div<br>
+<br>
+board-$(CONFIG_GENERIC) := generic<br>
+<br>
+KALLSYMS += --symbol-prefix=_<br>
+<br>
+archprepare: maketools<br>
+<br>
+PHONY += maketools<br>
+<br>
+ifneq ($(board-y),)<br>
+BOARD := arch/openrisc/boards/$(board-y)/<br>
+else<br>
+BOARD :=<br>
+endif<br>
+<br>
+common-y += $(BOARD)<br>
+common-y += arch/openrisc/lib/<br>
+common-y += arch/openrisc/cpu/<br>
+<br>
+lds-y += arch/openrisc/cpu/barebox.lds<br>
diff --git a/arch/openrisc/configs/generic_defconfig b/arch/openrisc/configs/generic_defconfig<br>
new file mode 100644<br>
index 0000000..68e0371<br>
--- /dev/null<br>
+++ b/arch/openrisc/configs/generic_defconfig<br>
@@ -0,0 +1,20 @@<br>
+CONFIG_LONGHELP=y<br>
+CONFIG_HUSH_FANCY_PROMPT=y<br>
+CONFIG_CMDLINE_EDITING=y<br>
+CONFIG_AUTO_COMPLETE=y<br>
+CONFIG_PARTITION=y<br>
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y<br>
+CONFIG_CMD_EDIT=y<br>
+CONFIG_CMD_SAVEENV=y<br>
+CONFIG_CMD_LOADENV=y<br>
+CONFIG_CMD_EXPORT=y<br>
+CONFIG_CMD_PRINTENV=y<br>
+CONFIG_CMD_TIME=y<br>
+CONFIG_CMD_MEMINFO=y<br>
+CONFIG_CMD_FLASH=y<br>
+# CONFIG_CMD_BOOTM is not set<br>
+CONFIG_CMD_RESET=y<br>
+CONFIG_CMD_GO=y<br>
+CONFIG_CMD_TIMEOUT=y<br>
+CONFIG_CMD_PARTITION=y<br>
+CONFIG_DRIVER_SERIAL_NS16550=y<br>
diff --git a/arch/openrisc/cpu/Makefile b/arch/openrisc/cpu/Makefile<br>
new file mode 100644<br>
index 0000000..1cd7506<br>
--- /dev/null<br>
+++ b/arch/openrisc/cpu/Makefile<br>
@@ -0,0 +1,5 @@<br>
+obj-y += start.o<br>
+obj-y += cpu.o<br>
+obj-y += exceptions.o<br>
+obj-y += cache.o<br>
+extra-y += barebox.lds<br>
diff --git a/arch/openrisc/cpu/barebox.lds.S b/arch/openrisc/cpu/barebox.lds.S<br>
new file mode 100644<br>
index 0000000..d3e02a6<br>
--- /dev/null<br>
+++ b/arch/openrisc/cpu/barebox.lds.S<br>
@@ -0,0 +1,98 @@<br>
+/*<br>
+ * barebox - barebox.lds.S<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#include <config.h><br>
+#include <asm-generic/barebox.lds.h><br>
+<br>
+OUTPUT_FORMAT("elf32-or32", "elf32-or32", "elf32-or32")<br>
+__DYNAMIC = 0;<br>
+<br>
+MEMORY<br>
+{<br>
+ vectors : ORIGIN = 0, LENGTH = 0x2000<br>
+ ram : ORIGIN = TEXT_BASE,<br>
+ LENGTH = BAREBOX_RESERVED_SIZE<br>
+}<br>
+<br>
+SECTIONS<br>
+{<br>
+ .vectors :<br>
+ {<br>
+ *(.vectors)<br>
+ } > vectors<br>
+<br>
+ . = ALIGN(4);<br>
+ __start = .;<br>
+ .text : AT (__start) {<br>
+ _stext = .;<br>
+ *(.text)<br>
+ _etext = .;<br>
+ *(.lit)<br>
+ *(.shdata)<br>
+ _endtext = .;<br>
+ } > ram<br>
+<br>
+ . = ALIGN(4);<br>
+ .rodata : {<br>
+ *(.rodata);<br>
+ *(.rodata.*)<br>
+ } > ram<br>
+<br>
+ . = ALIGN(4);<br>
+ . = .;<br>
+ __barebox_cmd_start = .;<br>
+ .barebox_cmd : { BAREBOX_CMDS } > ram<br>
+ __barebox_cmd_end = .;<br>
+<br>
+ __barebox_magicvar_start = .;<br>
+ .barebox_magicvar : { BAREBOX_MAGICVARS } > ram<br>
+ __barebox_magicvar_end = .;<br>
+<br>
+ __barebox_initcalls_start = .;<br>
+ .barebox_initcalls : { INITCALLS } > ram<br>
+ __barebox_initcalls_end = .;<br>
+<br>
+ ___usymtab_start = .;<br>
+ __usymtab : { BAREBOX_SYMS } > ram<br>
+ ___usymtab_end = .;<br>
+<br>
+ __etext = .; /* End of text and rodata section */<br>
+<br>
+ . = ALIGN(4);<br>
+ .data : {<br>
+ sdata = .;<br>
+ _sdata = .;<br>
+ *(.data)<br>
+ edata = .;<br>
+ _edata = .;<br>
+ } > ram<br>
+<br>
+ . = ALIGN(4);<br>
+ .bss :<br>
+ {<br>
+ __bss_start = .;<br>
+ _bss_start = .;<br>
+ *(.shbss)<br>
+ *(.bss)<br>
+ *(COMMON)<br>
+ _bss_end = .;<br>
+ __bss_stop = .;<br>
+ } > ram<br>
+ __end = .;<br>
+}<br>
diff --git a/arch/openrisc/cpu/cache.c b/arch/openrisc/cpu/cache.c<br>
new file mode 100644<br>
index 0000000..81a0d13<br>
--- /dev/null<br>
+++ b/arch/openrisc/cpu/cache.c<br>
@@ -0,0 +1,154 @@<br>
+/*<br>
+ * (C) Copyright 2011, Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>><br>
+ * (C) Copyright 2011, Julius Baxter <<a href="mailto:julius@opencores.org">julius@opencores.org</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#include <common.h><br>
+#include <init.h><br>
+#include <asm/system.h><br>
+<br>
+void flush_dcache_range(unsigned long addr, unsigned long stop)<br>
+{<br>
+ ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;<br>
+<br>
+ while (addr < stop) {<br>
+ mtspr(SPR_DCBFR, addr);<br>
+ addr += block_size;<br>
+ }<br>
+}<br>
+<br>
+void invalidate_dcache_range(unsigned long addr, unsigned long stop)<br>
+{<br>
+ ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;<br>
+<br>
+ while (addr < stop) {<br>
+ mtspr(SPR_DCBIR, addr);<br>
+ addr += block_size;<br>
+ }<br>
+}<br>
+<br>
+static void invalidate_icache_range(unsigned long addr, unsigned long stop)<br>
+{<br>
+ ulong block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16;<br>
+<br>
+ while (addr < stop) {<br>
+ mtspr(SPR_ICBIR, addr);<br>
+ addr += block_size;<br>
+ }<br>
+}<br>
+<br>
+void flush_cache(unsigned long addr, unsigned long size)<br>
+{<br>
+ flush_dcache_range(addr, addr + size);<br>
+ invalidate_icache_range(addr, addr + size);<br>
+}<br>
+<br>
+int icache_status(void)<br>
+{<br>
+ return mfspr(SPR_SR) & SPR_SR_ICE;<br>
+}<br>
+<br>
+int checkicache(void)<br>
+{<br>
+ unsigned long iccfgr;<br>
+ unsigned long cache_set_size;<br>
+ unsigned long cache_ways;<br>
+ unsigned long cache_block_size;<br>
+<br>
+ iccfgr = mfspr(SPR_ICCFGR);<br>
+ cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);<br>
+ cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);<br>
+ cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;<br>
+<br>
+ return cache_set_size * cache_ways * cache_block_size;<br>
+}<br>
+<br>
+int dcache_status(void)<br>
+{<br>
+ return mfspr(SPR_SR) & SPR_SR_DCE;<br>
+}<br>
+<br>
+int checkdcache(void)<br>
+{<br>
+ unsigned long dccfgr;<br>
+ unsigned long cache_set_size;<br>
+ unsigned long cache_ways;<br>
+ unsigned long cache_block_size;<br>
+<br>
+ dccfgr = mfspr(SPR_DCCFGR);<br>
+ cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);<br>
+ cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);<br>
+ cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;<br>
+<br>
+ return cache_set_size * cache_ways * cache_block_size;<br>
+}<br>
+<br>
+void dcache_enable(void)<br>
+{<br>
+ mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+}<br>
+<br>
+void dcache_disable(void)<br>
+{<br>
+ mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);<br>
+}<br>
+<br>
+void icache_enable(void)<br>
+{<br>
+ mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE);<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+ asm volatile("l.nop");<br>
+}<br>
+<br>
+void icache_disable(void)<br>
+{<br>
+ mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);<br>
+}<br>
+<br>
+int cache_init(void)<br>
+{<br>
+ if (mfspr(SPR_UPR) & SPR_UPR_ICP) {<br>
+ icache_disable();<br>
+ invalidate_icache_range(0, checkicache());<br>
+ icache_enable();<br>
+ }<br>
+<br>
+ if (mfspr(SPR_UPR) & SPR_UPR_DCP) {<br>
+ dcache_disable();<br>
+ invalidate_dcache_range(0, checkdcache());<br>
+ dcache_enable();<br>
+ }<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
+core_initcall(cache_init);<br>
diff --git a/arch/openrisc/cpu/cpu.c b/arch/openrisc/cpu/cpu.c<br>
new file mode 100644<br>
index 0000000..48f5d03<br>
--- /dev/null<br>
+++ b/arch/openrisc/cpu/cpu.c<br>
@@ -0,0 +1,43 @@<br>
+/*<br>
+ * (C) Copyright 2011, Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>><br>
+ * (C) Copyright 2011, Julius Baxter <<a href="mailto:julius@opencores.org">julius@opencores.org</a>><br>
+ *<br>
+ * See file CREDITS for list of people who contributed to this<br>
+ * project.<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#include <common.h><br>
+#include <init.h><br>
+#include <asm/system.h><br>
+#include <asm/openrisc_exc.h><br>
+<br>
+int cleanup_before_linux(void)<br>
+{<br>
+ return 0;<br>
+}<br>
+<br>
+extern void __reset(void);<br>
+<br>
+void __noreturn reset_cpu(ulong ignored)<br>
+{<br>
+ __reset();<br>
+ /* not reached, __reset does not return */<br>
+<br>
+ /* Not reached */<br>
+ while (1);<br>
+}<br>
diff --git a/arch/openrisc/cpu/exceptions.c b/arch/openrisc/cpu/exceptions.c<br>
new file mode 100644<br>
index 0000000..a979258<br>
--- /dev/null<br>
+++ b/arch/openrisc/cpu/exceptions.c<br>
@@ -0,0 +1,84 @@<br>
+/*<br>
+ * (C) Copyright 2011, Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>><br>
+ * (C) Copyright 2011, Julius Baxter <<a href="mailto:julius@opencores.org">julius@opencores.org</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#include <common.h><br>
+#include <asm/system.h><br>
+<br>
+static const char * const excp_table[] = {<br>
+ "Unknown exception",<br>
+ "Reset",<br>
+ "Bus Error",<br>
+ "Data Page Fault",<br>
+ "Instruction Page Fault",<br>
+ "Tick Timer",<br>
+ "Alignment",<br>
+ "Illegal Instruction",<br>
+ "External Interrupt",<br>
+ "D-TLB Miss",<br>
+ "I-TLB Miss",<br>
+ "Range",<br>
+ "System Call",<br>
+ "Floating Point",<br>
+ "Trap",<br>
+};<br>
+<br>
+static void (*handlers[32])(void);<br>
+<br>
+void exception_install_handler(int exception, void (*handler)(void))<br>
+{<br>
+ if (exception < 0 || exception > 31)<br>
+ return;<br>
+<br>
+ handlers[exception] = handler;<br>
+}<br>
+<br>
+void exception_free_handler(int exception)<br>
+{<br>
+ if (exception < 0 || exception > 31)<br>
+ return;<br>
+<br>
+ handlers[exception] = 0;<br>
+}<br>
+<br>
+static void exception_hang(int vect)<br>
+{<br>
+ printf("Unhandled exception at 0x%x ", vect & 0xff00);<br>
+<br>
+ vect = ((vect >> 8) & 0xff);<br>
+ if (vect < ARRAY_SIZE(excp_table))<br>
+ printf("(%s)\n", excp_table[vect]);<br>
+ else<br>
+ printf("(%s)\n", excp_table[0]);<br>
+<br>
+ printf("EPCR: 0x%08lx\n", mfspr(SPR_EPCR_BASE));<br>
+ printf("EEAR: 0x%08lx\n", mfspr(SPR_EEAR_BASE));<br>
+ printf("ESR: 0x%08lx\n", mfspr(SPR_ESR_BASE));<br>
+ hang();<br>
+}<br>
+<br>
+void exception_handler(int vect)<br>
+{<br>
+ int exception = vect >> 8;<br>
+<br>
+ if (handlers[exception])<br>
+ handlers[exception]();<br>
+ else<br>
+ exception_hang(vect);<br>
+}<br>
diff --git a/arch/openrisc/cpu/start.S b/arch/openrisc/cpu/start.S<br>
new file mode 100644<br>
index 0000000..056f116<br>
--- /dev/null<br>
+++ b/arch/openrisc/cpu/start.S<br>
@@ -0,0 +1,335 @@<br>
+/*<br>
+ * (C) Copyright 2011, Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>><br>
+ * (C) Copyright 2011, Julius Baxter <<a href="mailto:julius@opencores.org">julius@opencores.org</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#include <config.h><br>
+#include <asm-generic/memory_layout.h><br>
+#include <asm/spr-defs.h><br>
+<br>
+#define EXCEPTION_STACK_SIZE (128+128)<br>
+<br>
+#define HANDLE_EXCEPTION \<br>
+ l.addi r1, r1, -EXCEPTION_STACK_SIZE ;\<br>
+ l.sw 0x1c(r1), r9 ;\<br>
+ l.jal _exception_handler ;\<br>
+ l.nop ;\<br>
+ l.lwz r9, 0x1c(r1) ;\<br>
+ l.addi r1, r1, EXCEPTION_STACK_SIZE ;\<br>
+ l.rfe ;\<br>
+ l.nop<br>
+<br>
+ .section .vectors, "ax"<br>
+ .global __reset<br>
+<br>
+ /* reset */<br>
+ .org 0x100<br>
+__reset:<br>
+ /* there is no guarantee r0 is hardwired to zero, clear it here */<br>
+ l.andi r0, r0, 0<br>
+ /* reset stack and frame pointers */<br>
+ l.andi r1, r0, 0<br>
+ l.andi r2, r0, 0<br>
+<br>
+ /* set supervisor mode */<br>
+ l.ori r3,r0,SPR_SR_SM<br>
+ l.mtspr r0,r3,SPR_SR<br>
+<br>
+ /* Relocate barebox */<br>
+ l.movhi r3,hi(__start) /* source start address */<br>
+ l.ori r3,r3,lo(__start)<br>
+ l.movhi r4,hi(_stext) /* dest start address */<br>
+ l.ori r4,r4,lo(_stext)<br>
+ l.movhi r5,hi(__end) /* dest end address */<br>
+ l.ori r5,r5,lo(__end)<br>
+<br>
+.L_reloc:<br>
+ l.lwz r6,0(r3)<br>
+ l.sw 0(r4),r6<br>
+ l.addi r3,r3,4<br>
+ l.sfltu r4,r5<br>
+ <a href="http://l.bf" target="_blank">l.bf</a> .L_reloc<br>
+ l.addi r4,r4,4 /*delay slot */<br>
+<br>
+#ifdef CONFIG_SYS_RELOCATE_VECTORS<br>
+ /* Relocate vectors from 0xf0000000 to 0x00000000 */<br>
+ l.movhi r4, 0xf000 /* source */<br>
+ l.movhi r5, 0 /* destination */<br>
+ l.addi r6, r5, CONFIG_SYS_VECTORS_LEN /* length */<br>
+.L_relocvectors:<br>
+ l.lwz r7, 0(r4)<br>
+ l.sw 0(r5), r7<br>
+ l.addi r5, r5, 4<br>
+ l.sfeq r5,r6<br>
+ l.bnf .L_relocvectors<br>
+ l.addi r4,r4, 4<br>
+#endif<br>
+<br>
+ l.j _start<br>
+ l.nop<br>
+<br>
+ /* bus error */<br>
+ .org 0x200<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* data page fault */<br>
+ .org 0x300<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* instruction page fault */<br>
+ .org 0x400<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* tick timer */<br>
+ .org 0x500<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* alignment */<br>
+ .org 0x600<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* illegal instruction */<br>
+ .org 0x700<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* external interrupt */<br>
+ .org 0x800<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* D-TLB miss */<br>
+ .org 0x900<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* I-TLB miss */<br>
+ .org 0xa00<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* range */<br>
+ .org 0xb00<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* system call */<br>
+ .org 0xc00<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* floating point */<br>
+ .org 0xd00<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* trap */<br>
+ .org 0xe00<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0xf00<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1100<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1200<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1300<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1400<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1500<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1600<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1700<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1800<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1900<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1a00<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1b00<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1c00<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1d00<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1e00<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* reserved */<br>
+ .org 0x1f00<br>
+ HANDLE_EXCEPTION<br>
+<br>
+ /* Startup routine */<br>
+ .text<br>
+ .global _start<br>
+_start:<br>
+ /* Init stack and frame pointers */<br>
+ l.movhi r1, hi(STACK_BASE)<br>
+ l.ori r1, r1, lo(STACK_BASE)<br>
+ l.or r2, r0, r1<br>
+<br>
+ /* clear BSS segments */<br>
+ l.movhi r4, hi(_bss_start)<br>
+ l.ori r4, r4, lo(_bss_start)<br>
+ l.movhi r5, hi(_bss_end)<br>
+ l.ori r5, r5, lo(_bss_end)<br>
+.L_clear_bss:<br>
+ l.sw 0(r4), r0<br>
+ l.sfltu r4,r5<br>
+ <a href="http://l.bf" target="_blank">l.bf</a> .L_clear_bss<br>
+ l.addi r4,r4,4<br>
+<br>
+ /* Reset registers before jumping to board_init */<br>
+ l.andi r3, r0, 0<br>
+ l.andi r4, r0, 0<br>
+ l.andi r5, r0, 0<br>
+ l.andi r6, r0, 0<br>
+ l.andi r7, r0, 0<br>
+ l.andi r8, r0, 0<br>
+ l.andi r9, r0, 0<br>
+ l.andi r10, r0, 0<br>
+ l.andi r11, r0, 0<br>
+ l.andi r12, r0, 0<br>
+ l.andi r13, r0, 0<br>
+ l.andi r14, r0, 0<br>
+ l.andi r15, r0, 0<br>
+ l.andi r17, r0, 0<br>
+ l.andi r18, r0, 0<br>
+ l.andi r19, r0, 0<br>
+ l.andi r20, r0, 0<br>
+ l.andi r21, r0, 0<br>
+ l.andi r22, r0, 0<br>
+ l.andi r23, r0, 0<br>
+ l.andi r24, r0, 0<br>
+ l.andi r25, r0, 0<br>
+ l.andi r26, r0, 0<br>
+ l.andi r27, r0, 0<br>
+ l.andi r28, r0, 0<br>
+ l.andi r29, r0, 0<br>
+ l.andi r30, r0, 0<br>
+ l.andi r31, r0, 0<br>
+<br>
+ l.j start_barebox<br>
+ l.nop<br>
+<br>
+ .size _start, .-_start<br>
+<br>
+/*<br>
+ * Store state onto stack and call the real exception handler<br>
+ */<br>
+ .section .text<br>
+ .extern exception_handler<br>
+ .type _exception_handler,@function<br>
+<br>
+_exception_handler:<br>
+ /* Store state (r9 already saved)*/<br>
+ l.sw 0x00(r1), r2<br>
+ l.sw 0x04(r1), r3<br>
+ l.sw 0x08(r1), r4<br>
+ l.sw 0x0c(r1), r5<br>
+ l.sw 0x10(r1), r6<br>
+ l.sw 0x14(r1), r7<br>
+ l.sw 0x18(r1), r8<br>
+ l.sw 0x20(r1), r10<br>
+ l.sw 0x24(r1), r11<br>
+ l.sw 0x28(r1), r12<br>
+ l.sw 0x2c(r1), r13<br>
+ l.sw 0x30(r1), r14<br>
+ l.sw 0x34(r1), r15<br>
+ l.sw 0x38(r1), r16<br>
+ l.sw 0x3c(r1), r17<br>
+ l.sw 0x40(r1), r18<br>
+ l.sw 0x44(r1), r19<br>
+ l.sw 0x48(r1), r20<br>
+ l.sw 0x4c(r1), r21<br>
+ l.sw 0x50(r1), r22<br>
+ l.sw 0x54(r1), r23<br>
+ l.sw 0x58(r1), r24<br>
+ l.sw 0x5c(r1), r25<br>
+ l.sw 0x60(r1), r26<br>
+ l.sw 0x64(r1), r27<br>
+ l.sw 0x68(r1), r28<br>
+ l.sw 0x6c(r1), r29<br>
+ l.sw 0x70(r1), r30<br>
+ l.sw 0x74(r1), r31<br>
+<br>
+ /* Save return address */<br>
+ l.or r14, r0, r9<br>
+ /* Call exception handler with the link address as argument */<br>
+ l.jal exception_handler<br>
+ l.or r3, r0, r14<br>
+ /* Load return address */<br>
+ l.or r9, r0, r14<br>
+<br>
+ /* Restore state */<br>
+ l.lwz r2, 0x00(r1)<br>
+ l.lwz r3, 0x04(r1)<br>
+ l.lwz r4, 0x08(r1)<br>
+ l.lwz r5, 0x0c(r1)<br>
+ l.lwz r6, 0x10(r1)<br>
+ l.lwz r7, 0x14(r1)<br>
+ l.lwz r8, 0x18(r1)<br>
+ l.lwz r10, 0x20(r1)<br>
+ l.lwz r11, 0x24(r1)<br>
+ l.lwz r12, 0x28(r1)<br>
+ l.lwz r13, 0x2c(r1)<br>
+ l.lwz r14, 0x30(r1)<br>
+ l.lwz r15, 0x34(r1)<br>
+ l.lwz r16, 0x38(r1)<br>
+ l.lwz r17, 0x3c(r1)<br>
+ l.lwz r18, 0x40(r1)<br>
+ l.lwz r19, 0x44(r1)<br>
+ l.lwz r20, 0x48(r1)<br>
+ l.lwz r21, 0x4c(r1)<br>
+ l.lwz r22, 0x50(r1)<br>
+ l.lwz r23, 0x54(r1)<br>
+ l.lwz r24, 0x58(r1)<br>
+ l.lwz r25, 0x5c(r1)<br>
+ l.lwz r26, 0x60(r1)<br>
+ l.lwz r27, 0x64(r1)<br>
+ l.lwz r28, 0x68(r1)<br>
+ l.lwz r29, 0x6c(r1)<br>
+ l.lwz r30, 0x70(r1)<br>
+ l.lwz r31, 0x74(r1)<br>
+ l.jr r9<br>
+ l.nop<br>
diff --git a/arch/openrisc/include/asm/barebox.h b/arch/openrisc/include/asm/barebox.h<br>
new file mode 100644<br>
index 0000000..9dd1df8<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/barebox.h<br>
@@ -0,0 +1,4 @@<br>
+#ifndef _ASM_BAREBOX_H_<br>
+#define _ASM_BAREBOX_H_<br>
+<br>
+#endif /* _ASM_BAREBOX_H_ */<br>
diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h<br>
new file mode 100644<br>
index 0000000..c001a5d<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/bitops.h<br>
@@ -0,0 +1,28 @@<br>
+/*<br>
+ * (C) Copyright 2011, Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#ifndef __ASM_OPENRISC_BITOPS_H<br>
+#define __ASM_OPENRISC_BITOPS_H<br>
+<br>
+#define PLATFORM_FLS<br>
+#include <asm/bitops/fls.h><br>
+#define PLATFORM_FFS<br>
+#include <asm/bitops/ffs.h><br>
+<br>
+#endif /* __ASM_GENERIC_BITOPS_H */<br>
diff --git a/arch/openrisc/include/asm/bitops/ffs.h b/arch/openrisc/include/asm/bitops/ffs.h<br>
new file mode 100644<br>
index 0000000..1de5295<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/bitops/ffs.h<br>
@@ -0,0 +1,26 @@<br>
+/*<br>
+ * OpenRISC Linux<br>
+ *<br>
+ * Copyright (C) 2010-2011 Jonas Bonn <<a href="mailto:jonas@southpole.se">jonas@southpole.se</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; either version 2 of the License, or<br>
+ * (at your option) any later version.<br>
+ */<br>
+<br>
+#ifndef __ASM_OPENRISC_FFS_H<br>
+#define __ASM_OPENRISC_FFS_H<br>
+<br>
+static inline int ffs(int x)<br>
+{<br>
+ int ret;<br>
+<br>
+ __asm__ ("l.ff1 %0,%1"<br>
+ : "=r" (ret)<br>
+ : "r" (x));<br>
+<br>
+ return ret;<br>
+}<br>
+<br>
+#endif /* __ASM_OPENRISC_FFS_H */<br>
diff --git a/arch/openrisc/include/asm/bitops/fls.h b/arch/openrisc/include/asm/bitops/fls.h<br>
new file mode 100644<br>
index 0000000..8c77c13<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/bitops/fls.h<br>
@@ -0,0 +1,26 @@<br>
+/*<br>
+ * OpenRISC Linux<br>
+ *<br>
+ * Copyright (C) 2010-2011 Jonas Bonn <<a href="mailto:jonas@southpole.se">jonas@southpole.se</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; either version 2 of the License, or<br>
+ * (at your option) any later version.<br>
+ */<br>
+<br>
+#ifndef __ASM_OPENRISC_FLS_H<br>
+#define __ASM_OPENRISC_FLS_H<br>
+<br>
+static inline int fls(int x)<br>
+{<br>
+ int ret;<br>
+<br>
+ __asm__ ("l.fl1 %0,%1"<br>
+ : "=r" (ret)<br>
+ : "r" (x));<br>
+<br>
+ return ret;<br>
+}<br>
+<br>
+#endif /* __ASM_OPENRISC_FLS_H */<br>
diff --git a/arch/openrisc/include/asm/byteorder.h b/arch/openrisc/include/asm/byteorder.h<br>
new file mode 100644<br>
index 0000000..60d14f7<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/byteorder.h<br>
@@ -0,0 +1 @@<br>
+#include <linux/byteorder/big_endian.h><br>
diff --git a/arch/openrisc/include/asm/cache.h b/arch/openrisc/include/asm/cache.h<br>
new file mode 100644<br>
index 0000000..05cf998<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/cache.h<br>
@@ -0,0 +1,47 @@<br>
+/*<br>
+ * (C) Copyright 2011, Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#ifndef __ASM_OPENRISC_CACHE_H_<br>
+#define __ASM_OPENRISC_CACHE_H_<br>
+<br>
+void flush_dcache_range(unsigned long addr, unsigned long stop);<br>
+void invalidate_dcache_range(unsigned long addr, unsigned long stop);<br>
+void flush_cache(unsigned long addr, unsigned long size);<br>
+int icache_status(void);<br>
+int checkicache(void);<br>
+int dcache_status(void);<br>
+int checkdcache(void);<br>
+void dcache_enable(void);<br>
+void dcache_disable(void);<br>
+void icache_enable(void);<br>
+void icache_disable(void);<br>
+<br>
+/*<br>
+ * Valid L1 data cache line sizes for the OpenRISC architecture are<br>
+ * 16 and 32 bytes.<br>
+ * If the board configuration has not specified one we default to the<br>
+ * largest of these values for alignment of DMA buffers.<br>
+ */<br>
+#ifdef CONFIG_SYS_CACHELINE_SIZE<br>
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE<br>
+#else<br>
+#define ARCH_DMA_MINALIGN 32<br>
+#endif<br>
+<br>
+#endif /* __ASM_OPENRISC_CACHE_H_ */<br>
diff --git a/arch/openrisc/include/asm/common.h b/arch/openrisc/include/asm/common.h<br>
new file mode 100644<br>
index 0000000..027dca2<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/common.h<br>
@@ -0,0 +1,4 @@<br>
+#ifndef _ASM_COMMON_H<br>
+#define __ASM_COMMON_H<br>
+<br>
+#endif /* _ASM_COMMON_H */<br>
diff --git a/arch/openrisc/include/asm/elf.h b/arch/openrisc/include/asm/elf.h<br>
new file mode 100644<br>
index 0000000..6a134a5<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/elf.h<br>
@@ -0,0 +1,107 @@<br>
+/*<br>
+ * OpenRISC Linux<br>
+ *<br>
+ * Linux architectural port borrowing liberally from similar works of<br>
+ * others. All original copyrights apply as per the original source<br>
+ * declaration.<br>
+ *<br>
+ * OpenRISC implementation:<br>
+ * Copyright (C) 2003 Matjaz Breskvar <<a href="mailto:phoenix@bsemi.com">phoenix@bsemi.com</a>><br>
+ * Copyright (C) 2010-2011 Jonas Bonn <<a href="mailto:jonas@southpole.se">jonas@southpole.se</a>><br>
+ * et al.<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; either version 2 of the License, or<br>
+ * (at your option) any later version.<br>
+ */<br>
+<br>
+#ifndef __ASM_OPENRISC_ELF_H<br>
+#define __ASM_OPENRISC_ELF_H<br>
+<br>
+/*<br>
+ * ELF register definitions..<br>
+ */<br>
+#include <linux/types.h><br>
+#include <asm/ptrace.h><br>
+<br>
+/* The OR1K relocation types... not all relevant for module loader */<br>
+#define R_OR32_NONE 0<br>
+#define R_OR32_32 1<br>
+#define R_OR32_16 2<br>
+#define R_OR32_8 3<br>
+#define R_OR32_CONST 4<br>
+#define R_OR32_CONSTH 5<br>
+#define R_OR32_JUMPTARG 6<br>
+#define R_OR32_VTINHERIT 7<br>
+#define R_OR32_VTENTRY 8<br>
+<br>
+typedef unsigned long elf_greg_t;<br>
+<br>
+/*<br>
+ * Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is<br>
+ * thus exposed to user-space.<br>
+ */<br>
+#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))<br>
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];<br>
+<br>
+/* A placeholder; OR32 does not have fp support yes, so no fp regs for now. */<br>
+typedef unsigned long elf_fpregset_t;<br>
+<br>
+/* This should be moved to include/linux/elf.h */<br>
+#define EM_OR32 0x8472<br>
+#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */<br>
+<br>
+/*<br>
+ * These are used to set parameters in the core dumps.<br>
+ */<br>
+#define ELF_ARCH EM_OR32<br>
+#define ELF_CLASS ELFCLASS32<br>
+#define ELF_DATA ELFDATA2MSB<br>
+<br>
+#ifdef __KERNEL__<br>
+<br>
+/*<br>
+ * This is used to ensure we don't load something for the wrong architecture.<br>
+ */<br>
+<br>
+#define elf_check_arch(x) \<br>
+ (((x)->e_machine == EM_OR32) || ((x)->e_machine == EM_OPENRISC))<br>
+<br>
+/* This is the location that an ET_DYN program is loaded if exec'ed. Typical<br>
+ use of this is to invoke "./ld.so someprog" to test out a new version of<br>
+ the loader. We need to make sure that it is out of the way of the program<br>
+ that it will "exec", and that there is sufficient room for the brk. */<br>
+<br>
+#define ELF_ET_DYN_BASE (0x08000000)<br>
+<br>
+/*<br>
+ * Enable dump using regset.<br>
+ * This covers all of general/DSP/FPU regs.<br>
+ */<br>
+#define CORE_DUMP_USE_REGSET<br>
+<br>
+#define ELF_EXEC_PAGESIZE 8192<br>
+<br>
+extern void dump_elf_thread(elf_greg_t *dest, struct pt_regs *pt);<br>
+#define ELF_CORE_COPY_REGS(dest, regs) dump_elf_thread(dest, regs);<br>
+<br>
+/* This yields a mask that user programs can use to figure out what<br>
+ instruction set this cpu supports. This could be done in userspace,<br>
+ but it's not easy, and we've already done it here. */<br>
+<br>
+#define ELF_HWCAP (0)<br>
+<br>
+/* This yields a string that ld.so will use to load implementation<br>
+ specific libraries for optimization. This is more specific in<br>
+ intent than poking at uname or /proc/cpuinfo.<br>
+<br>
+ For the moment, we have only optimizations for the Intel generations,<br>
+ but that could change... */<br>
+<br>
+#define ELF_PLATFORM (NULL)<br>
+<br>
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)<br>
+<br>
+#endif /* __KERNEL__ */<br>
+#endif<br>
diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h<br>
new file mode 100644<br>
index 0000000..19b260a<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/io.h<br>
@@ -0,0 +1,123 @@<br>
+/*<br>
+ * (C) Copyright 2011, Julius Baxter <<a href="mailto:julius@opencores.org">julius@opencores.org</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#ifndef __ASM_OPENRISC_IO_H<br>
+#define __ASM_OPENRISC_IO_H<br>
+<br>
+#include <asm/byteorder.h><br>
+<br>
+/*<br>
+ * Given a physical address and a length, return a virtual address<br>
+ * that can be used to access the memory range with the caching<br>
+ * properties specified by "flags".<br>
+ */<br>
+#define MAP_NOCACHE (0)<br>
+#define MAP_WRCOMBINE (0)<br>
+#define MAP_WRBACK (0)<br>
+#define MAP_WRTHROUGH (0)<br>
+<br>
+static inline void *<br>
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)<br>
+{<br>
+ return (void *)paddr;<br>
+}<br>
+<br>
+/*<br>
+ * Take down a mapping set up by map_physmem().<br>
+ */<br>
+static inline void unmap_physmem(void *vaddr, unsigned long flags)<br>
+{<br>
+<br>
+}<br>
+<br>
+/*<br>
+ * Change virtual addresses to physical addresses<br>
+ */<br>
+static inline phys_addr_t virt_to_phys(void *vaddr)<br>
+{<br>
+ return (phys_addr_t)(vaddr);<br>
+}<br>
+<br>
+<br>
+/*<br>
+ * readX/writeX() are used to access memory mapped devices. On some<br>
+ * architectures the memory mapped IO stuff needs to be accessed<br>
+ * differently. On the openrisc architecture, we just read/write the<br>
+ * memory location directly.<br>
+ */<br>
+#define readb(addr) (*(volatile unsigned char *) (addr))<br>
+#define readw(addr) (*(volatile unsigned short *) (addr))<br>
+#define readl(addr) (*(volatile unsigned int *) (addr))<br>
+#define __raw_readb readb<br>
+#define __raw_readw readw<br>
+#define __raw_readl readl<br>
+<br>
+#define writeb(b, addr) ((*(volatile unsigned char *) (addr)) = (b))<br>
+#define writew(b, addr) ((*(volatile unsigned short *) (addr)) = (b))<br>
+#define writel(b, addr) ((*(volatile unsigned int *) (addr)) = (b))<br>
+#define __raw_writeb writeb<br>
+#define __raw_writew writew<br>
+#define __raw_writel writel<br>
+<br>
+#define memset_io(a, b, c) memset((void *)(a), (b), (c))<br>
+#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))<br>
+#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))<br>
+<br>
+#define out_be32(a, v) __raw_writel((v), (void __iomem __force *)(a))<br>
+#define out_be16(a, v) __raw_writew((v), (a))<br>
+<br>
+#define in_be32(a) __raw_readl((const void __iomem __force *)(a))<br>
+#define in_be16(a) __raw_readw(a)<br>
+<br>
+#define writel_be(v, a) out_be32((__force unsigned *)a, v)<br>
+#define readl_be(a) in_be32((__force unsigned *)a)<br>
+<br>
+/*<br>
+ * Again, OpenRISC does not require mem IO specific function.<br>
+ */<br>
+<br>
+<br>
+#define IO_BASE 0x0<br>
+#define IO_SPACE_LIMIT 0xffffffff<br>
+<br>
+#define inb(port) readb((port + IO_BASE))<br>
+#define outb(value, port) writeb((value), (port + IO_BASE))<br>
+#define inb_p(port) inb((port))<br>
+#define outb_p(value, port) outb((value), (port))<br>
+<br>
+/*<br>
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem<br>
+ * access<br>
+ */<br>
+#define xlate_dev_mem_ptr(p) __va(p)<br>
+<br>
+/*<br>
+ * Convert a virtual cached pointer to an uncached pointer<br>
+ */<br>
+#define xlate_dev_kmem_ptr(p) p<br>
+<br>
+#define ioread8(addr) readb(addr)<br>
+#define ioread16(addr) readw(addr)<br>
+#define ioread32(addr) readl(addr)<br>
+<br>
+#define iowrite8(v, addr) writeb((v), (addr))<br>
+#define iowrite16(v, addr) writew((v), (addr))<br>
+#define iowrite32(v, addr) writel((v), (addr))<br>
+<br>
+#endif<br>
diff --git a/arch/openrisc/include/asm/openrisc_exc.h b/arch/openrisc/include/asm/openrisc_exc.h<br>
new file mode 100644<br>
index 0000000..33f6453<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/openrisc_exc.h<br>
@@ -0,0 +1,41 @@<br>
+/*<br>
+ * (C) Copyright 2011, Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#ifndef _OPENRISC_EXC_H_<br>
+#define _OPENRISC_EXC_H_<br>
+<br>
+#define EXC_RESET 0x01<br>
+#define EXC_BUS_ERROR 0x02<br>
+#define EXC_DATA_PAGE_FAULT 0x03<br>
+#define EXC_INSTR_PAGE_FAULT 0x04<br>
+#define EXC_TIMER 0x05<br>
+#define EXC_ALIGNMENT 0x06<br>
+#define EXC_ILLEGAL_INSTR 0x07<br>
+#define EXC_EXT_IRQ 0x08<br>
+#define EXC_DTLB_MISS 0x09<br>
+#define EXC_ITLB_MISS 0x0a<br>
+#define EXC_RANGE 0x0b<br>
+#define EXC_SYSCALL 0x0c<br>
+#define EXC_FLOAT_POINT 0x0d<br>
+#define EXC_TRAP 0x0e<br>
+<br>
+void exception_install_handler(int exception, void (*handler)(void));<br>
+void exception_free_handler(int exception);<br>
+<br>
+#endif<br>
diff --git a/arch/openrisc/include/asm/posix_types.h b/arch/openrisc/include/asm/posix_types.h<br>
new file mode 100644<br>
index 0000000..7f4c942<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/posix_types.h<br>
@@ -0,0 +1,71 @@<br>
+/*<br>
+ * Based on microblaze implementation:<br>
+ * Copyright (C) 2003 John Williams <<a href="mailto:jwilliams@itee.uq.edu.au">jwilliams@itee.uq.edu.au</a>><br>
+ * Copyright (C) 2001,2002 NEC Corporation<br>
+ * Copyright (C) 2001,2002 Miles Bader <<a href="mailto:miles@gnu.org">miles@gnu.org</a>><br>
+ *<br>
+ * This file is subject to the terms and conditions of the GNU General<br>
+ * Public License. See the file COPYING in the main directory of this<br>
+ * archive for more details.<br>
+ *<br>
+ * Written by Miles Bader <<a href="mailto:miles@gnu.org">miles@gnu.org</a>><br>
+ * Microblaze port by John Williams<br>
+ */<br>
+<br>
+#ifndef __ASM_OPENRISC_POSIX_TYPES_H<br>
+#define __ASM_OPENRISC_POSIX_TYPES_H<br>
+<br>
+typedef unsigned long __kernel_ino_t;<br>
+typedef unsigned long long __kernel_ino64_t;<br>
+typedef unsigned int __kernel_mode_t;<br>
+typedef unsigned int __kernel_nlink_t;<br>
+typedef long __kernel_off_t;<br>
+typedef long long __kernel_loff_t;<br>
+typedef int __kernel_pid_t;<br>
+typedef unsigned short __kernel_ipc_pid_t;<br>
+typedef unsigned int __kernel_uid_t;<br>
+typedef unsigned int __kernel_gid_t;<br>
+typedef unsigned int __kernel_size_t;<br>
+typedef int __kernel_ssize_t;<br>
+typedef int __kernel_ptrdiff_t;<br>
+typedef long __kernel_time_t;<br>
+typedef long __kernel_suseconds_t;<br>
+typedef long __kernel_clock_t;<br>
+typedef int __kernel_daddr_t;<br>
+typedef char *__kernel_caddr_t;<br>
+typedef unsigned short __kernel_uid16_t;<br>
+typedef unsigned short __kernel_gid16_t;<br>
+typedef unsigned int __kernel_uid32_t;<br>
+typedef unsigned int __kernel_gid32_t;<br>
+<br>
+typedef unsigned short __kernel_old_uid_t;<br>
+typedef unsigned short __kernel_old_gid_t;<br>
+<br>
+<br>
+typedef struct {<br>
+#if defined(__KERNEL__) || defined(__USE_ALL)<br>
+ int val[2];<br>
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */<br>
+ int __val[2];<br>
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */<br>
+} __kernel_fsid_t;<br>
+<br>
+<br>
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)<br>
+<br>
+#undef __FD_SET<br>
+#define __FD_SET(fd, fd_set) \<br>
+ __set_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)<br>
+#undef __FD_CLR<br>
+#define __FD_CLR(fd, fd_set) \<br>
+ __clear_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)<br>
+#undef __FD_ISSET<br>
+#define __FD_ISSET(fd, fd_set) \<br>
+ __test_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)<br>
+#undef __FD_ZERO<br>
+#define __FD_ZERO(fd_set) \<br>
+ memset(fd_set, 0, sizeof(*(fd_set *)fd_set))<br>
+<br>
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */<br>
+<br>
+#endif /* __ASM_OPENRISC_POSIX_TYPES_H */<br>
diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm/ptrace.h<br>
new file mode 100644<br>
index 0000000..ffdea52<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/ptrace.h<br>
@@ -0,0 +1,131 @@<br>
+/*<br>
+ * OpenRISC Linux<br>
+ *<br>
+ * Linux architectural port borrowing liberally from similar works of<br>
+ * others. All original copyrights apply as per the original source<br>
+ * declaration.<br>
+ *<br>
+ * OpenRISC implementation:<br>
+ * Copyright (C) 2003 Matjaz Breskvar <<a href="mailto:phoenix@bsemi.com">phoenix@bsemi.com</a>><br>
+ * Copyright (C) 2010-2011 Jonas Bonn <<a href="mailto:jonas@southpole.se">jonas@southpole.se</a>><br>
+ * et al.<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; either version 2 of the License, or<br>
+ * (at your option) any later version.<br>
+ */<br>
+<br>
+#ifndef __ASM_OPENRISC_PTRACE_H<br>
+#define __ASM_OPENRISC_PTRACE_H<br>
+<br>
+#include <asm/spr-defs.h><br>
+<br>
+#ifndef __ASSEMBLY__<br>
+/*<br>
+ * This is the layout of the regset returned by the GETREGSET ptrace call<br>
+ */<br>
+struct user_regs_struct {<br>
+ /* GPR R0-R31... */<br>
+ unsigned long gpr[32];<br>
+ unsigned long pc;<br>
+ unsigned long sr;<br>
+ unsigned long pad1;<br>
+ unsigned long pad2;<br>
+};<br>
+#endif<br>
+<br>
+#ifdef __KERNEL__<br>
+<br>
+/*<br>
+ * Make kernel PTrace/register structures opaque to userspace... userspace can<br>
+ * access thread state via the regset mechanism. This allows us a bit of<br>
+ * flexibility in how we order the registers on the stack, permitting some<br>
+ * optimizations like packing call-clobbered registers together so that<br>
+ * they share a cacheline (not done yet, though... future optimization).<br>
+ */<br>
+<br>
+#ifndef __ASSEMBLY__<br>
+/*<br>
+ * This struct describes how the registers are laid out on the kernel stack<br>
+ * during a syscall or other kernel entry.<br>
+ *<br>
+ * This structure should always be cacheline aligned on the stack.<br>
+ * FIXME: I don't think that's the case right now. The alignment is<br>
+ * taken care of elsewhere... head.S, process.c, etc.<br>
+ */<br>
+<br>
+struct pt_regs {<br>
+ union {<br>
+ struct {<br>
+ /* Named registers */<br>
+ long sr; /* Stored in place of r0 */<br>
+ long sp; /* r1 */<br>
+ };<br>
+ struct {<br>
+ /* Old style */<br>
+ long offset[2];<br>
+ long gprs[30];<br>
+ };<br>
+ struct {<br>
+ /* New style */<br>
+ long gpr[32];<br>
+ };<br>
+ };<br>
+ long pc;<br>
+ long orig_gpr11; /* For restarting system calls */<br>
+ long syscallno; /* Syscall number (used by strace) */<br>
+ long dummy; /* Cheap alignment fix */<br>
+};<br>
+#endif /* __ASSEMBLY__ */<br>
+<br>
+/* TODO: Rename this to REDZONE because that's what it is */<br>
+#define STACK_FRAME_OVERHEAD 128 /* size of minimum stack frame */<br>
+<br>
+#define instruction_pointer(regs) ((regs)->pc)<br>
+#define user_mode(regs) (((regs)->sr & SPR_SR_SM) == 0)<br>
+#define user_stack_pointer(regs) ((unsigned long)(regs)->sp)<br>
+#define profile_pc(regs) instruction_pointer(regs)<br>
+<br>
+/*<br>
+ * Offsets used by 'ptrace' system call interface.<br>
+ */<br>
+#define PT_SR 0<br>
+#define PT_SP 4<br>
+#define PT_GPR2 8<br>
+#define PT_GPR3 12<br>
+#define PT_GPR4 16<br>
+#define PT_GPR5 20<br>
+#define PT_GPR6 24<br>
+#define PT_GPR7 28<br>
+#define PT_GPR8 32<br>
+#define PT_GPR9 36<br>
+#define PT_GPR10 40<br>
+#define PT_GPR11 44<br>
+#define PT_GPR12 48<br>
+#define PT_GPR13 52<br>
+#define PT_GPR14 56<br>
+#define PT_GPR15 60<br>
+#define PT_GPR16 64<br>
+#define PT_GPR17 68<br>
+#define PT_GPR18 72<br>
+#define PT_GPR19 76<br>
+#define PT_GPR20 80<br>
+#define PT_GPR21 84<br>
+#define PT_GPR22 88<br>
+#define PT_GPR23 92<br>
+#define PT_GPR24 96<br>
+#define PT_GPR25 100<br>
+#define PT_GPR26 104<br>
+#define PT_GPR27 108<br>
+#define PT_GPR28 112<br>
+#define PT_GPR29 116<br>
+#define PT_GPR30 120<br>
+#define PT_GPR31 124<br>
+#define PT_PC 128<br>
+#define PT_ORIG_GPR11 132<br>
+#define PT_SYSCALLNO 136<br>
+<br>
+#endif /* __KERNEL__ */<br>
+<br>
+#endif /* __ASM_OPENRISC_PTRACE_H */<br>
diff --git a/arch/openrisc/include/asm/sections.h b/arch/openrisc/include/asm/sections.h<br>
new file mode 100644<br>
index 0000000..2b8c516<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/sections.h<br>
@@ -0,0 +1 @@<br>
+#include <asm-generic/sections.h><br>
diff --git a/arch/openrisc/include/asm/spr-defs.h b/arch/openrisc/include/asm/spr-defs.h<br>
new file mode 100644<br>
index 0000000..cb0cdfa<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/spr-defs.h<br>
@@ -0,0 +1,567 @@<br>
+/*<br>
+ * SPR Definitions<br>
+ *<br>
+ * Copyright (C) 2000 Damjan Lampret<br>
+ * Copyright (C) 2003 Matjaz Breskvar <<a href="mailto:phoenix@bsemi.com">phoenix@bsemi.com</a>><br>
+ * Copyright (C) 2008, 2010 Embecosm Limited<br>
+ * Copyright (C) 2010-2011 Jonas Bonn <<a href="mailto:jonas@southpole.se">jonas@southpole.se</a>><br>
+ * et al.<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; either version 2 of the License, or<br>
+ * (at your option) any later version.<br>
+ *<br>
+ * This file is part of OpenRISC 1000 Architectural Simulator.<br>
+ */<br>
+<br>
+#ifndef SPR_DEFS__H<br>
+#define SPR_DEFS__H<br>
+<br>
+/* Definition of special-purpose registers (SPRs) */<br>
+<br>
+#define MAX_GRPS (32)<br>
+#define MAX_SPRS_PER_GRP_BITS (11)<br>
+#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)<br>
+#define MAX_SPRS (0x10000)<br>
+<br>
+/* Base addresses for the groups */<br>
+#define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)<br>
+#define SPRGROUP_DMMU (1 << MAX_SPRS_PER_GRP_BITS)<br>
+#define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS)<br>
+#define SPRGROUP_DC (3 << MAX_SPRS_PER_GRP_BITS)<br>
+#define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS)<br>
+#define SPRGROUP_MAC (5 << MAX_SPRS_PER_GRP_BITS)<br>
+#define SPRGROUP_D (6 << MAX_SPRS_PER_GRP_BITS)<br>
+#define SPRGROUP_PC (7 << MAX_SPRS_PER_GRP_BITS)<br>
+#define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS)<br>
+#define SPRGROUP_PIC (9 << MAX_SPRS_PER_GRP_BITS)<br>
+#define SPRGROUP_TT (10 << MAX_SPRS_PER_GRP_BITS)<br>
+#define SPRGROUP_FP (11 << MAX_SPRS_PER_GRP_BITS)<br>
+<br>
+/* System control and status group */<br>
+#define SPR_VR (SPRGROUP_SYS + 0)<br>
+#define SPR_UPR (SPRGROUP_SYS + 1)<br>
+#define SPR_CPUCFGR (SPRGROUP_SYS + 2)<br>
+#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)<br>
+#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)<br>
+#define SPR_DCCFGR (SPRGROUP_SYS + 5)<br>
+#define SPR_ICCFGR (SPRGROUP_SYS + 6)<br>
+#define SPR_DCFGR (SPRGROUP_SYS + 7)<br>
+#define SPR_PCCFGR (SPRGROUP_SYS + 8)<br>
+#define SPR_NPC (SPRGROUP_SYS + 16)<br>
+#define SPR_SR (SPRGROUP_SYS + 17)<br>
+#define SPR_PPC (SPRGROUP_SYS + 18)<br>
+#define SPR_FPCSR (SPRGROUP_SYS + 20)<br>
+#define SPR_EPCR_BASE (SPRGROUP_SYS + 32)<br>
+#define SPR_EPCR_LAST (SPRGROUP_SYS + 47)<br>
+#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)<br>
+#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)<br>
+#define SPR_ESR_BASE (SPRGROUP_SYS + 64)<br>
+#define SPR_ESR_LAST (SPRGROUP_SYS + 79)<br>
+#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)<br>
+<br>
+/* Data MMU group */<br>
+#define SPR_DMMUCR (SPRGROUP_DMMU + 0)<br>
+#define SPR_DTLBEIR (SPRGROUP_DMMU + 2)<br>
+#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)<br>
+#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)<br>
+#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)<br>
+#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)<br>
+<br>
+/* Instruction MMU group */<br>
+#define SPR_IMMUCR (SPRGROUP_IMMU + 0)<br>
+#define SPR_ITLBEIR (SPRGROUP_IMMU + 2)<br>
+#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)<br>
+#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)<br>
+#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)<br>
+#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)<br>
+<br>
+/* Data cache group */<br>
+#define SPR_DCCR (SPRGROUP_DC + 0)<br>
+#define SPR_DCBPR (SPRGROUP_DC + 1)<br>
+#define SPR_DCBFR (SPRGROUP_DC + 2)<br>
+#define SPR_DCBIR (SPRGROUP_DC + 3)<br>
+#define SPR_DCBWR (SPRGROUP_DC + 4)<br>
+#define SPR_DCBLR (SPRGROUP_DC + 5)<br>
+#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)<br>
+#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)<br>
+<br>
+/* Instruction cache group */<br>
+#define SPR_ICCR (SPRGROUP_IC + 0)<br>
+#define SPR_ICBPR (SPRGROUP_IC + 1)<br>
+#define SPR_ICBIR (SPRGROUP_IC + 2)<br>
+#define SPR_ICBLR (SPRGROUP_IC + 3)<br>
+#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)<br>
+#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)<br>
+<br>
+/* MAC group */<br>
+#define SPR_MACLO (SPRGROUP_MAC + 1)<br>
+#define SPR_MACHI (SPRGROUP_MAC + 2)<br>
+<br>
+/* Debug group */<br>
+#define SPR_DVR(N) (SPRGROUP_D + (N))<br>
+#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))<br>
+#define SPR_DMR1 (SPRGROUP_D + 16)<br>
+#define SPR_DMR2 (SPRGROUP_D + 17)<br>
+#define SPR_DWCR0 (SPRGROUP_D + 18)<br>
+#define SPR_DWCR1 (SPRGROUP_D + 19)<br>
+#define SPR_DSR (SPRGROUP_D + 20)<br>
+#define SPR_DRR (SPRGROUP_D + 21)<br>
+<br>
+/* Performance counters group */<br>
+#define SPR_PCCR(N) (SPRGROUP_PC + (N))<br>
+#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))<br>
+<br>
+/* Power management group */<br>
+#define SPR_PMR (SPRGROUP_PM + 0)<br>
+<br>
+/* PIC group */<br>
+#define SPR_PICMR (SPRGROUP_PIC + 0)<br>
+#define SPR_PICPR (SPRGROUP_PIC + 1)<br>
+#define SPR_PICSR (SPRGROUP_PIC + 2)<br>
+<br>
+/* Tick Timer group */<br>
+#define SPR_TTMR (SPRGROUP_TT + 0)<br>
+#define SPR_TTCR (SPRGROUP_TT + 1)<br>
+<br>
+/*<br>
+ * Bit definitions for the Version Register<br>
+ */<br>
+#define SPR_VR_VER 0xff000000 /* Processor version */<br>
+#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */<br>
+#define SPR_VR_RES 0x0000ffc0 /* Reserved */<br>
+#define SPR_VR_REV 0x0000003f /* Processor revision */<br>
+<br>
+#define SPR_VR_VER_OFF 24<br>
+#define SPR_VR_CFG_OFF 16<br>
+#define SPR_VR_REV_OFF 0<br>
+<br>
+/*<br>
+ * Bit definitions for the Unit Present Register<br>
+ */<br>
+#define SPR_UPR_UP 0x00000001 /* UPR present */<br>
+#define SPR_UPR_DCP 0x00000002 /* Data cache present */<br>
+#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */<br>
+#define SPR_UPR_DMP 0x00000008 /* Data MMU present */<br>
+#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */<br>
+#define SPR_UPR_MP 0x00000020 /* MAC present */<br>
+#define SPR_UPR_DUP 0x00000040 /* Debug unit present */<br>
+#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */<br>
+#define SPR_UPR_PMP 0x00000100 /* Power management present */<br>
+#define SPR_UPR_PICP 0x00000200 /* PIC present */<br>
+#define SPR_UPR_TTP 0x00000400 /* Tick timer present */<br>
+#define SPR_UPR_RES 0x00fe0000 /* Reserved */<br>
+#define SPR_UPR_CUP 0xff000000 /* Context units present */<br>
+<br>
+/*<br>
+ * Bit definitions for the CPU configuration register<br>
+ */<br>
+#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */<br>
+#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */<br>
+#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */<br>
+#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */<br>
+#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */<br>
+#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */<br>
+#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */<br>
+#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */<br>
+<br>
+/*<br>
+ * Bit definitions for the Debug configuration register and other<br>
+ * constants.<br>
+ */<br>
+<br>
+#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */<br>
+#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */<br>
+#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */<br>
+#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */<br>
+#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */<br>
+#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */<br>
+#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */<br>
+#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */<br>
+#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */<br>
+#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */<br>
+<br>
+#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \<br>
+ 2 == n ? SPR_DCFGR_NDP2 : \<br>
+ 3 == n ? SPR_DCFGR_NDP3 : \<br>
+ 4 == n ? SPR_DCFGR_NDP4 : \<br>
+ 5 == n ? SPR_DCFGR_NDP5 : \<br>
+ 6 == n ? SPR_DCFGR_NDP6 : \<br>
+ 7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)<br>
+#define MAX_MATCHPOINTS 8<br>
+#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2)<br>
+<br>
+/*<br>
+ * Bit definitions for the Supervision Register<br>
+ */<br>
+#define SPR_SR_SM 0x00000001 /* Supervisor Mode */<br>
+#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */<br>
+#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */<br>
+#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */<br>
+#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */<br>
+#define SPR_SR_DME 0x00000020 /* Data MMU Enable */<br>
+#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */<br>
+#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */<br>
+#define SPR_SR_CE 0x00000100 /* CID Enable */<br>
+#define SPR_SR_F 0x00000200 /* Condition Flag */<br>
+#define SPR_SR_CY 0x00000400 /* Carry flag */<br>
+#define SPR_SR_OV 0x00000800 /* Overflow flag */<br>
+#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */<br>
+#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */<br>
+#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */<br>
+#define SPR_SR_FO 0x00008000 /* Fixed one */<br>
+#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */<br>
+#define SPR_SR_RES 0x0ffe0000 /* Reserved */<br>
+#define SPR_SR_CID 0xf0000000 /* Context ID */<br>
+<br>
+/*<br>
+ * Bit definitions for the Data MMU Control Register<br>
+ */<br>
+#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */<br>
+#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */<br>
+#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */<br>
+#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */<br>
+<br>
+/*<br>
+ * Bit definitions for the Instruction MMU Control Register<br>
+ */<br>
+#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */<br>
+#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */<br>
+#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */<br>
+#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */<br>
+<br>
+/*<br>
+ * Bit definitions for the Data TLB Match Register<br>
+ */<br>
+#define SPR_DTLBMR_V 0x00000001 /* Valid */<br>
+#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */<br>
+#define SPR_DTLBMR_CID 0x0000003c /* Context ID */<br>
+#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */<br>
+#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */<br>
+<br>
+/*<br>
+ * Bit definitions for the Data TLB Translate Register<br>
+ */<br>
+#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */<br>
+#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */<br>
+#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */<br>
+#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */<br>
+#define SPR_DTLBTR_A 0x00000010 /* Accessed */<br>
+#define SPR_DTLBTR_D 0x00000020 /* Dirty */<br>
+#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */<br>
+#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */<br>
+#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */<br>
+#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */<br>
+#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */<br>
+<br>
+/*<br>
+ * Bit definitions for the Instruction TLB Match Register<br>
+ */<br>
+#define SPR_ITLBMR_V 0x00000001 /* Valid */<br>
+#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */<br>
+#define SPR_ITLBMR_CID 0x0000003c /* Context ID */<br>
+#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */<br>
+#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */<br>
+<br>
+/*<br>
+ * Bit definitions for the Instruction TLB Translate Register<br>
+ */<br>
+#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */<br>
+#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */<br>
+#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */<br>
+#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */<br>
+#define SPR_ITLBTR_A 0x00000010 /* Accessed */<br>
+#define SPR_ITLBTR_D 0x00000020 /* Dirty */<br>
+#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */<br>
+#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */<br>
+#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */<br>
+<br>
+/*<br>
+ * Bit definitions for Data Cache Control register<br>
+ */<br>
+#define SPR_DCCR_EW 0x000000ff /* Enable ways */<br>
+<br>
+/*<br>
+ * Bit definitions for Insn Cache Control register<br>
+ */<br>
+#define SPR_ICCR_EW 0x000000ff /* Enable ways */<br>
+<br>
+/*<br>
+ * Bit definitions for Data Cache Configuration Register<br>
+ */<br>
+<br>
+#define SPR_DCCFGR_NCW 0x00000007<br>
+#define SPR_DCCFGR_NCS 0x00000078<br>
+#define SPR_DCCFGR_CBS 0x00000080<br>
+#define SPR_DCCFGR_CWS 0x00000100<br>
+#define SPR_DCCFGR_CCRI 0x00000200<br>
+#define SPR_DCCFGR_CBIRI 0x00000400<br>
+#define SPR_DCCFGR_CBPRI 0x00000800<br>
+#define SPR_DCCFGR_CBLRI 0x00001000<br>
+#define SPR_DCCFGR_CBFRI 0x00002000<br>
+#define SPR_DCCFGR_CBWBRI 0x00004000<br>
+<br>
+#define SPR_DCCFGR_NCW_OFF 0<br>
+#define SPR_DCCFGR_NCS_OFF 3<br>
+#define SPR_DCCFGR_CBS_OFF 7<br>
+<br>
+/*<br>
+ * Bit definitions for Instruction Cache Configuration Register<br>
+ */<br>
+#define SPR_ICCFGR_NCW 0x00000007<br>
+#define SPR_ICCFGR_NCS 0x00000078<br>
+#define SPR_ICCFGR_CBS 0x00000080<br>
+#define SPR_ICCFGR_CCRI 0x00000200<br>
+#define SPR_ICCFGR_CBIRI 0x00000400<br>
+#define SPR_ICCFGR_CBPRI 0x00000800<br>
+#define SPR_ICCFGR_CBLRI 0x00001000<br>
+<br>
+#define SPR_ICCFGR_NCW_OFF 0<br>
+#define SPR_ICCFGR_NCS_OFF 3<br>
+#define SPR_ICCFGR_CBS_OFF 7<br>
+<br>
+/*<br>
+ * Bit definitions for Data MMU Configuration Register<br>
+ */<br>
+#define SPR_DMMUCFGR_NTW 0x00000003<br>
+#define SPR_DMMUCFGR_NTS 0x0000001C<br>
+#define SPR_DMMUCFGR_NAE 0x000000E0<br>
+#define SPR_DMMUCFGR_CRI 0x00000100<br>
+#define SPR_DMMUCFGR_PRI 0x00000200<br>
+#define SPR_DMMUCFGR_TEIRI 0x00000400<br>
+#define SPR_DMMUCFGR_HTR 0x00000800<br>
+<br>
+#define SPR_DMMUCFGR_NTW_OFF 0<br>
+#define SPR_DMMUCFGR_NTS_OFF 2<br>
+<br>
+/*<br>
+ * Bit definitions for Instruction MMU Configuration Register<br>
+ */<br>
+#define SPR_IMMUCFGR_NTW 0x00000003<br>
+#define SPR_IMMUCFGR_NTS 0x0000001C<br>
+#define SPR_IMMUCFGR_NAE 0x000000E0<br>
+#define SPR_IMMUCFGR_CRI 0x00000100<br>
+#define SPR_IMMUCFGR_PRI 0x00000200<br>
+#define SPR_IMMUCFGR_TEIRI 0x00000400<br>
+#define SPR_IMMUCFGR_HTR 0x00000800<br>
+<br>
+#define SPR_IMMUCFGR_NTW_OFF 0<br>
+#define SPR_IMMUCFGR_NTS_OFF 2<br>
+<br>
+/*<br>
+ * Bit definitions for Debug Control registers<br>
+ */<br>
+#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */<br>
+#define SPR_DCR_CC 0x0000000e /* Compare condition */<br>
+#define SPR_DCR_SC 0x00000010 /* Signed compare */<br>
+#define SPR_DCR_CT 0x000000e0 /* Compare to */<br>
+<br>
+/* Bit results with SPR_DCR_CC mask */<br>
+#define SPR_DCR_CC_MASKED 0x00000000<br>
+#define SPR_DCR_CC_EQUAL 0x00000002<br>
+#define SPR_DCR_CC_LESS 0x00000004<br>
+#define SPR_DCR_CC_LESSE 0x00000006<br>
+#define SPR_DCR_CC_GREAT 0x00000008<br>
+#define SPR_DCR_CC_GREATE 0x0000000a<br>
+#define SPR_DCR_CC_NEQUAL 0x0000000c<br>
+<br>
+/* Bit results with SPR_DCR_CT mask */<br>
+#define SPR_DCR_CT_DISABLED 0x00000000<br>
+#define SPR_DCR_CT_IFEA 0x00000020<br>
+#define SPR_DCR_CT_LEA 0x00000040<br>
+#define SPR_DCR_CT_SEA 0x00000060<br>
+#define SPR_DCR_CT_LD 0x00000080<br>
+#define SPR_DCR_CT_SD 0x000000a0<br>
+#define SPR_DCR_CT_LSEA 0x000000c0<br>
+#define SPR_DCR_CT_LSD 0x000000e0<br>
+<br>
+/*<br>
+ * Bit definitions for Debug Mode 1 register<br>
+ */<br>
+#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */<br>
+#define SPR_DMR1_CW0_AND 0x00000001<br>
+#define SPR_DMR1_CW0_OR 0x00000002<br>
+#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)<br>
+#define SPR_DMR1_CW1_AND 0x00000004<br>
+#define SPR_DMR1_CW1_OR 0x00000008<br>
+#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)<br>
+#define SPR_DMR1_CW2_AND 0x00000010<br>
+#define SPR_DMR1_CW2_OR 0x00000020<br>
+#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)<br>
+#define SPR_DMR1_CW3_AND 0x00000040<br>
+#define SPR_DMR1_CW3_OR 0x00000080<br>
+#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)<br>
+#define SPR_DMR1_CW4_AND 0x00000100<br>
+#define SPR_DMR1_CW4_OR 0x00000200<br>
+#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)<br>
+#define SPR_DMR1_CW5_AND 0x00000400<br>
+#define SPR_DMR1_CW5_OR 0x00000800<br>
+#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)<br>
+#define SPR_DMR1_CW6_AND 0x00001000<br>
+#define SPR_DMR1_CW6_OR 0x00002000<br>
+#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)<br>
+#define SPR_DMR1_CW7_AND 0x00004000<br>
+#define SPR_DMR1_CW7_OR 0x00008000<br>
+#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)<br>
+#define SPR_DMR1_CW8_AND 0x00010000<br>
+#define SPR_DMR1_CW8_OR 0x00020000<br>
+#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)<br>
+#define SPR_DMR1_CW9_AND 0x00040000<br>
+#define SPR_DMR1_CW9_OR 0x00080000<br>
+#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)<br>
+#define SPR_DMR1_RES1 0x00300000 /* Reserved */<br>
+#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/<br>
+#define SPR_DMR1_BT 0x00800000 /* Branch trace */<br>
+#define SPR_DMR1_RES2 0xff000000 /* Reserved */<br>
+<br>
+/*<br>
+ * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB<br>
+ */<br>
+#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */<br>
+#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */<br>
+#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */<br>
+#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */<br>
+#define SPR_DMR2_WGB 0x003ff000 /* Watch generating breakpoint */<br>
+#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */<br>
+#define SPR_DMR2_WBS 0xffc00000 /* Watchpoint status */<br>
+#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */<br>
+<br>
+/*<br>
+ * Bit definitions for Debug watchpoint counter registers<br>
+ */<br>
+#define SPR_DWCR_COUNT 0x0000ffff /* Count */<br>
+#define SPR_DWCR_MATCH 0xffff0000 /* Match */<br>
+#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */<br>
+<br>
+/*<br>
+ * Bit definitions for Debug stop register<br>
+ *<br>
+ */<br>
+#define SPR_DSR_RSTE 0x00000001 /* Reset exception */<br>
+#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */<br>
+#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */<br>
+#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */<br>
+#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */<br>
+#define SPR_DSR_AE 0x00000020 /* Alignment exception */<br>
+#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */<br>
+#define SPR_DSR_IE 0x00000080 /* Interrupt exception */<br>
+#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */<br>
+#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */<br>
+#define SPR_DSR_RE 0x00000400 /* Range exception */<br>
+#define SPR_DSR_SCE 0x00000800 /* System call exception */<br>
+#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */<br>
+#define SPR_DSR_TE 0x00002000 /* Trap exception */<br>
+<br>
+/*<br>
+ * Bit definitions for Debug reason register<br>
+ */<br>
+#define SPR_DRR_RSTE 0x00000001 /* Reset exception */<br>
+#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */<br>
+#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */<br>
+#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */<br>
+#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */<br>
+#define SPR_DRR_AE 0x00000020 /* Alignment exception */<br>
+#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */<br>
+#define SPR_DRR_IE 0x00000080 /* Interrupt exception */<br>
+#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */<br>
+#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */<br>
+#define SPR_DRR_RE 0x00000400 /* Range exception */<br>
+#define SPR_DRR_SCE 0x00000800 /* System call exception */<br>
+#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */<br>
+#define SPR_DRR_TE 0x00002000 /* Trap exception */<br>
+<br>
+/*<br>
+ * Bit definitions for Performance counters mode registers<br>
+ */<br>
+#define SPR_PCMR_CP 0x00000001 /* Counter present */<br>
+#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */<br>
+#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */<br>
+#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */<br>
+#define SPR_PCMR_LA 0x00000010 /* Load access event */<br>
+#define SPR_PCMR_SA 0x00000020 /* Store access event */<br>
+#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/<br>
+#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */<br>
+#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */<br>
+#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */<br>
+#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */<br>
+#define SPR_PCMR_BS 0x00000800 /* Branch stall event */<br>
+#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */<br>
+#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */<br>
+#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */<br>
+#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */<br>
+<br>
+/*<br>
+ * Bit definitions for the Power management register<br>
+ */<br>
+#define SPR_PMR_SDF 0x0000000f /* Slow down factor */<br>
+#define SPR_PMR_DME 0x00000010 /* Doze mode enable */<br>
+#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */<br>
+#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */<br>
+#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */<br>
+<br>
+/*<br>
+ * Bit definitions for PICMR<br>
+ */<br>
+#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */<br>
+<br>
+/*<br>
+ * Bit definitions for PICPR<br>
+ */<br>
+#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */<br>
+<br>
+/*<br>
+ * Bit definitions for PICSR<br>
+ */<br>
+#define SPR_PICSR_IS 0xffffffff /* Interrupt status */<br>
+<br>
+/*<br>
+ * Bit definitions for Tick Timer Control Register<br>
+ */<br>
+#define SPR_TTCR_CNT 0xffffffff /* Count, time period */<br>
+#define SPR_TTMR_TP 0x0fffffff /* Time period */<br>
+#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */<br>
+#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */<br>
+#define SPR_TTMR_DI 0x00000000 /* Disabled */<br>
+#define SPR_TTMR_RT 0x40000000 /* Restart tick */<br>
+#define SPR_TTMR_SR 0x80000000 /* Single run */<br>
+#define SPR_TTMR_CR 0xc0000000 /* Continuous run */<br>
+#define SPR_TTMR_M 0xc0000000 /* Tick mode */<br>
+<br>
+/*<br>
+ * Bit definitions for the FP Control Status Register<br>
+ */<br>
+#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */<br>
+#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */<br>
+#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */<br>
+#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */<br>
+#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */<br>
+#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */<br>
+#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */<br>
+#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */<br>
+#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */<br>
+#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */<br>
+#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */<br>
+#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \<br>
+ SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \<br>
+ SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)<br>
+<br>
+#define FPCSR_RM_RN (0<<1)<br>
+#define FPCSR_RM_RZ (1<<1)<br>
+#define FPCSR_RM_RIP (2<<1)<br>
+#define FPCSR_RM_RIN (3<<1)<br>
+<br>
+/*<br>
+ * l.nop constants<br>
+ */<br>
+#define NOP_NOP 0x0000 /* Normal nop instruction */<br>
+#define NOP_EXIT 0x0001 /* End of simulation */<br>
+#define NOP_REPORT 0x0002 /* Simple report */<br>
+#define NOP_PUTC 0x0004 /* Simputc instruction */<br>
+#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */<br>
+#define NOP_GET_TICKS 0x0006 /* Get # ticks running */<br>
+#define NOP_GET_PS 0x0007 /* Get picosecs/cycle */<br>
+#define NOP_REPORT_FIRST 0x0400 /* Report with number */<br>
+#define NOP_REPORT_LAST 0x03ff /* Report with number */<br>
+<br>
+#endif /* SPR_DEFS__H */<br>
diff --git a/arch/openrisc/include/asm/string.h b/arch/openrisc/include/asm/string.h<br>
new file mode 100644<br>
index 0000000..73e2655<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/string.h<br>
@@ -0,0 +1,4 @@<br>
+#ifndef __ASM_OPENRISC_STRING_H<br>
+#define __ASM_OPENRISC_STRING_H<br>
+<br>
+#endif<br>
diff --git a/arch/openrisc/include/asm/swab.h b/arch/openrisc/include/asm/swab.h<br>
new file mode 100644<br>
index 0000000..b07e1d5<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/swab.h<br>
@@ -0,0 +1,4 @@<br>
+#ifndef _ASM_SWAB_H<br>
+#define _ASM_SWAB_H<br>
+<br>
+#endif /* _ASM_SWAB_H */<br>
diff --git a/arch/openrisc/include/asm/system.h b/arch/openrisc/include/asm/system.h<br>
new file mode 100644<br>
index 0000000..d680363<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/system.h<br>
@@ -0,0 +1,39 @@<br>
+/*<br>
+ * (C) Copyright 2011, Julius Baxter <<a href="mailto:julius@opencores.org">julius@opencores.org</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#ifndef __ASM_OPENRISC_SYSTEM_H<br>
+#define __ASM_OPENRISC_SYSTEM_H<br>
+<br>
+#include <asm/spr-defs.h><br>
+<br>
+static inline unsigned long mfspr(unsigned long add)<br>
+{<br>
+ unsigned long ret;<br>
+<br>
+ __asm__ __volatile__ ("l.mfspr %0,r0,%1" : "=r" (ret) : "K" (add));<br>
+<br>
+ return ret;<br>
+}<br>
+<br>
+static inline void mtspr(unsigned long add, unsigned long val)<br>
+{<br>
+ __asm__ __volatile__ ("l.mtspr r0,%1,%0" : : "K" (add), "r" (val));<br>
+}<br>
+<br>
+#endif /* __ASM_OPENRISC_SYSTEM_H */<br>
diff --git a/arch/openrisc/include/asm/types.h b/arch/openrisc/include/asm/types.h<br>
new file mode 100644<br>
index 0000000..55efa36<br>
--- /dev/null<br>
+++ b/arch/openrisc/include/asm/types.h<br>
@@ -0,0 +1,79 @@<br>
+/*<br>
+ * (C) Copyright 2011, Julius Baxter <<a href="mailto:julius@opencores.org">julius@opencores.org</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#ifndef _ASM_TYPES_H<br>
+#define _ASM_TYPES_H<br>
+<br>
+/*<br>
+ * This file is never included by application software unless<br>
+ * explicitly requested (e.g., via linux/types.h) in which case the<br>
+ * application is Linux specific so (user-) name space pollution is<br>
+ * not a major issue. However, for interoperability, libraries still<br>
+ * need to be careful to avoid a name clashes.<br>
+ */<br>
+<br>
+typedef unsigned short umode_t;<br>
+<br>
+/*<br>
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the<br>
+ * header files exported to user space<br>
+ */<br>
+<br>
+typedef __signed__ char __s8;<br>
+typedef unsigned char __u8;<br>
+<br>
+typedef __signed__ short __s16;<br>
+typedef unsigned short __u16;<br>
+<br>
+typedef __signed__ int __s32;<br>
+typedef unsigned int __u32;<br>
+<br>
+#if defined(__GNUC__)<br>
+__extension__ typedef __signed__ long long __s64;<br>
+__extension__ typedef unsigned long long __u64;<br>
+#endif<br>
+<br>
+/*<br>
+ * These aren't exported outside the kernel to avoid name space clashes<br>
+ */<br>
+#ifdef __KERNEL__<br>
+<br>
+typedef signed char s8;<br>
+typedef unsigned char u8;<br>
+<br>
+typedef signed short s16;<br>
+typedef unsigned short u16;<br>
+<br>
+typedef signed int s32;<br>
+typedef unsigned int u32;<br>
+<br>
+typedef signed long long s64;<br>
+typedef unsigned long long u64;<br>
+<br>
+#define BITS_PER_LONG 32<br>
+<br>
+/* Dma addresses are 32-bits wide. */<br>
+<br>
+typedef u32 dma_addr_t;<br>
+<br>
+/*typedef unsigned long phys_addr_t;*/<br>
+typedef unsigned long phys_size_t;<br>
+#endif /* __KERNEL__ */<br>
+<br>
+#endif /* _ASM_TYPES_H */<br>
diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile<br>
new file mode 100644<br>
index 0000000..aaf93cb<br>
--- /dev/null<br>
+++ b/arch/openrisc/lib/Makefile<br>
@@ -0,0 +1,6 @@<br>
+obj-y += clock.o<br>
+obj-y += board.o<br>
+obj-y += cpuinfo.o<br>
+obj-y += muldi3.o<br>
+obj-y += lshrdi3.o<br>
+obj-y += ashldi3.o<br>
diff --git a/arch/openrisc/lib/ashldi3.S b/arch/openrisc/lib/ashldi3.S<br>
new file mode 100644<br>
index 0000000..3e422fa<br>
--- /dev/null<br>
+++ b/arch/openrisc/lib/ashldi3.S<br>
@@ -0,0 +1,41 @@<br>
+/*<br>
+ * (C) Copyright 2011 - Franck JULLIEN <<a href="mailto:elec4fun@gmail.com">elec4fun@gmail.com</a>><br>
+ *<br>
+ * Extracted from gcc generated assembly.<br>
+ *<br>
+ * Extended precision shifts.<br>
+ *<br>
+ * R3/R4 (MSW, LSW) has 64 bit value<br>
+ * R5 has shift count<br>
+ * result in R11/R12<br>
+ *<br>
+ */<br>
+<br>
+.globl __ashldi3<br>
+<br>
+__ashldi3:<br>
+ l.sfeqi r5,0x0<br>
+ <a href="http://l.bf" target="_blank">l.bf</a> out /* if count = 0, go out */<br>
+<br>
+ l.addi r6,r0,0x20 /* r6 = 32 */<br>
+ l.sub r6,r6,r5 /* r6 = 32 - count */<br>
+ l.sfgtsi r6,0x0 /* if count >= 32 */<br>
+ l.bnf more_than_32 /* branch to more_than_32 */<br>
+ l.nop 0x0<br>
+<br>
+less_than_32:<br>
+ l.srl r6,r4,r6 /* r6 gets the bits moved from LSW to MSW */<br>
+ l.sll r3,r3,r5 /* shift MSW */<br>
+ l.sll r4,r4,r5 /* shift LSW */<br>
+ l.or r3,r6,r3 /* MSW gets bits shifted from LSW */<br>
+<br>
+out:<br>
+ l.ori r11,r3,0x0<br>
+ l.jr r9<br>
+ l.ori r12,r4,0x0<br>
+<br>
+more_than_32:<br>
+ l.sub r3,r0,r6 /* r3 = -r6, the number of bits above 32 */<br>
+ l.sll r3,r4,r3 /* MSW = LSW << r3 */<br>
+ l.j out /* go out */<br>
+ l.addi r4,r0,0x0 /* LSW = 0 */<br>
diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c<br>
new file mode 100644<br>
index 0000000..a2158cb<br>
--- /dev/null<br>
+++ b/arch/openrisc/lib/board.c<br>
@@ -0,0 +1,42 @@<br>
+/*<br>
+ * (C) Copyright 2011 - Franck JULLIEN <<a href="mailto:elec4fun@gmail.com">elec4fun@gmail.com</a>><br>
+ *<br>
+ * See file CREDITS for list of people who contributed to this<br>
+ * project.<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#include <common.h><br>
+#include <malloc.h><br>
+#include <init.h><br>
+#include <memory.h><br>
+#include <asm-generic/memory_layout.h><br>
+<br>
+int openrisc_mem_malloc_init(void)<br>
+{<br>
+<br>
+ mem_malloc_init((void *)(OPENRISC_SOPC_TEXT_BASE - MALLOC_SIZE),<br>
+ (void *)(OPENRISC_SOPC_TEXT_BASE - 1));<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
+core_initcall(openrisc_mem_malloc_init);<br>
+<br>
+void arch_shutdown(void)<br>
+{<br>
+}<br>
diff --git a/arch/openrisc/lib/clock.c b/arch/openrisc/lib/clock.c<br>
new file mode 100644<br>
index 0000000..ab0a90d<br>
--- /dev/null<br>
+++ b/arch/openrisc/lib/clock.c<br>
@@ -0,0 +1,50 @@<br>
+/*<br>
+ * (C) Copyright 2011 - Franck JULLIEN <<a href="mailto:elec4fun@gmail.com">elec4fun@gmail.com</a>><br>
+ *<br>
+ * See file CREDITS for list of people who contributed to this<br>
+ * project.<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#include <common.h><br>
+#include <clock.h><br>
+#include <init.h><br>
+#include <asm/system.h><br>
+#include <asm/openrisc_exc.h><br>
+<br>
+static uint64_t openrisc_clocksource_read(void)<br>
+{<br>
+ return (uint64_t)(mfspr(SPR_TTCR));<br>
+}<br>
+<br>
+static struct clocksource cs = {<br>
+ .read = openrisc_clocksource_read,<br>
+ .mask = 0xffffffff,<br>
+ .shift = 12,<br>
+};<br>
+<br>
+static int clocksource_init(void)<br>
+{<br>
+ mtspr(SPR_TTMR, SPR_TTMR_CR | 0xFFFFFF);<br>
+ cs.mult = clocksource_hz2mult(OPENRISC_TIMER_FREQ, cs.shift);<br>
+<br>
+ init_clock(&cs);<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
+core_initcall(clocksource_init);<br>
diff --git a/arch/openrisc/lib/cpuinfo.c b/arch/openrisc/lib/cpuinfo.c<br>
new file mode 100644<br>
index 0000000..3ec44c1<br>
--- /dev/null<br>
+++ b/arch/openrisc/lib/cpuinfo.c<br>
@@ -0,0 +1,156 @@<br>
+/*<br>
+ * (C) Copyright 2011, Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>><br>
+ * (C) Copyright 2011, Julius Baxter <<a href="mailto:julius@opencores.org">julius@opencores.org</a>><br>
+ *<br>
+ * See file CREDITS for list of people who contributed to this<br>
+ * project.<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU General Public License as<br>
+ * published by the Free Software Foundation; either version 2 of<br>
+ * the License, or (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,<br>
+ * MA 02111-1307 USA<br>
+ */<br>
+<br>
+#include <common.h><br>
+#include <command.h><br>
+#include <asm/system.h><br>
+#include <asm/cache.h><br>
+#include <asm/openrisc_exc.h><br>
+<br>
+static volatile int illegal_instruction;<br>
+<br>
+static void illegal_instruction_handler(void)<br>
+{<br>
+ ulong *epcr = (ulong *)mfspr(SPR_EPCR_BASE);<br>
+<br>
+ /* skip over the illegal instruction */<br>
+ mtspr(SPR_EPCR_BASE, (ulong)(++epcr));<br>
+ illegal_instruction = 1;<br>
+}<br>
+<br>
+static int checkinstructions(void)<br>
+{<br>
+ ulong ra = 1, rb = 1, rc;<br>
+<br>
+ exception_install_handler(EXC_ILLEGAL_INSTR,<br>
+ illegal_instruction_handler);<br>
+<br>
+ illegal_instruction = 0;<br>
+ asm volatile("l.mul %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));<br>
+ printf(" Hardware multiplier: %s\n",<br>
+ illegal_instruction ? "no" : "yes");<br>
+<br>
+ illegal_instruction = 0;<br>
+ asm volatile("l.div %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));<br>
+ printf(" Hardware divider: %s\n",<br>
+ illegal_instruction ? "no" : "yes");<br>
+<br>
+ exception_free_handler(EXC_ILLEGAL_INSTR);<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
+int checkcpu(void)<br>
+{<br>
+ ulong upr = mfspr(SPR_UPR);<br>
+ ulong vr = mfspr(SPR_VR);<br>
+ ulong iccfgr = mfspr(SPR_ICCFGR);<br>
+ ulong dccfgr = mfspr(SPR_DCCFGR);<br>
+ ulong immucfgr = mfspr(SPR_IMMUCFGR);<br>
+ ulong dmmucfgr = mfspr(SPR_DMMUCFGR);<br>
+ ulong cpucfgr = mfspr(SPR_CPUCFGR);<br>
+ uint ver = (vr & SPR_VR_VER) >> 24;<br>
+ uint rev = vr & SPR_VR_REV;<br>
+ uint block_size;<br>
+ uint ways;<br>
+ uint sets;<br>
+<br>
+ printf("CPU: OpenRISC-%x00 (rev %d) @ %d MHz\n",<br>
+ ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000));<br>
+<br>
+ if (upr & SPR_UPR_DCP) {<br>
+ block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;<br>
+ ways = 1 << (dccfgr & SPR_DCCFGR_NCW);<br>
+ printf(" D-Cache: %d bytes, %d bytes/line, %d way(s)\n",<br>
+ checkdcache(), block_size, ways);<br>
+ } else {<br>
+ printf(" D-Cache: no\n");<br>
+ }<br>
+<br>
+ if (upr & SPR_UPR_ICP) {<br>
+ block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;<br>
+ ways = 1 << (iccfgr & SPR_ICCFGR_NCW);<br>
+ printf(" I-Cache: %d bytes, %d bytes/line, %d way(s)\n",<br>
+ checkicache(), block_size, ways);<br>
+ } else {<br>
+ printf(" I-Cache: no\n");<br>
+ }<br>
+<br>
+ if (upr & SPR_UPR_DMP) {<br>
+ sets = 1 << ((dmmucfgr & SPR_DMMUCFGR_NTS) >> 2);<br>
+ ways = (dmmucfgr & SPR_DMMUCFGR_NTW) + 1;<br>
+ printf(" DMMU: %d sets, %d way(s)\n",<br>
+ sets, ways);<br>
+ } else {<br>
+ printf(" DMMU: no\n");<br>
+ }<br>
+<br>
+ if (upr & SPR_UPR_IMP) {<br>
+ sets = 1 << ((immucfgr & SPR_IMMUCFGR_NTS) >> 2);<br>
+ ways = (immucfgr & SPR_IMMUCFGR_NTW) + 1;<br>
+ printf(" IMMU: %d sets, %d way(s)\n",<br>
+ sets, ways);<br>
+ } else {<br>
+ printf(" IMMU: no\n");<br>
+ }<br>
+<br>
+ printf(" MAC unit: %s\n",<br>
+ (upr & SPR_UPR_MP) ? "yes" : "no");<br>
+ printf(" Debug unit: %s\n",<br>
+ (upr & SPR_UPR_DUP) ? "yes" : "no");<br>
+ printf(" Performance counters: %s\n",<br>
+ (upr & SPR_UPR_PCUP) ? "yes" : "no");<br>
+ printf(" Power management: %s\n",<br>
+ (upr & SPR_UPR_PMP) ? "yes" : "no");<br>
+ printf(" Interrupt controller: %s\n",<br>
+ (upr & SPR_UPR_PICP) ? "yes" : "no");<br>
+ printf(" Timer: %s\n",<br>
+ (upr & SPR_UPR_TTP) ? "yes" : "no");<br>
+ printf(" Custom unit(s): %s\n",<br>
+ (upr & SPR_UPR_CUP) ? "yes" : "no");<br>
+<br>
+ printf(" Supported instructions:\n");<br>
+ printf(" ORBIS32: %s\n",<br>
+ (cpucfgr & SPR_CPUCFGR_OB32S) ? "yes" : "no");<br>
+ printf(" ORBIS64: %s\n",<br>
+ (cpucfgr & SPR_CPUCFGR_OB64S) ? "yes" : "no");<br>
+ printf(" ORFPX32: %s\n",<br>
+ (cpucfgr & SPR_CPUCFGR_OF32S) ? "yes" : "no");<br>
+ printf(" ORFPX64: %s\n",<br>
+ (cpucfgr & SPR_CPUCFGR_OF64S) ? "yes" : "no");<br>
+<br>
+ checkinstructions();<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
+static int do_cpuinfo(struct command *cmdtp, int argc, char *argv[])<br>
+{<br>
+ checkcpu();<br>
+ return 0;<br>
+}<br>
+<br>
+BAREBOX_CMD_START(cpuinfo)<br>
+ .cmd = do_cpuinfo,<br>
+ .usage = "Show info about CPU",<br>
+BAREBOX_CMD_END<br>
diff --git a/arch/openrisc/lib/lshrdi3.S b/arch/openrisc/lib/lshrdi3.S<br>
new file mode 100644<br>
index 0000000..de30445<br>
--- /dev/null<br>
+++ b/arch/openrisc/lib/lshrdi3.S<br>
@@ -0,0 +1,41 @@<br>
+/*<br>
+ * (C) Copyright 2011 - Franck JULLIEN <<a href="mailto:elec4fun@gmail.com">elec4fun@gmail.com</a>><br>
+ *<br>
+ * Extracted from gcc generated assembly.<br>
+ *<br>
+ * Extended precision shifts.<br>
+ *<br>
+ * R3/R4 (MSW, LSW) has 64 bit value<br>
+ * R5 has shift count<br>
+ * result in R11/R12<br>
+ *<br>
+ */<br>
+<br>
+.globl __lshrdi3<br>
+<br>
+__lshrdi3:<br>
+ l.sfeqi r5,0x0<br>
+ <a href="http://l.bf" target="_blank">l.bf</a> out /* if count = 0, go out */<br>
+<br>
+ l.addi r6,r0,0x20 /* r6 = 32 */<br>
+ l.sub r6,r6,r5 /* r6 = 32 - count */<br>
+ l.sfgtsi r6,0x0 /* if count >= 32 */<br>
+ l.bnf more_than_32 /* branch to more_than_32 */<br>
+ l.nop 0x0<br>
+<br>
+less_than_32:<br>
+ l.sll r6,r3,r6 /* r6 gets the bits moved from MSW to LSW */<br>
+ l.srl r4,r4,r5 /* shift LSW */<br>
+ l.srl r3,r3,r5 /* shift MSW */<br>
+ l.or r4,r6,r4 /* LSW gets bits shifted from MSW */<br>
+<br>
+ out:<br>
+ l.ori r11,r3,0x0<br>
+ l.jr r9<br>
+ l.ori r12,r4,0x0<br>
+<br>
+more_than_32:<br>
+ l.sub r4,r0,r6 /* r4 = -r6, the number of bits above 32 */<br>
+ l.srl r4,r3,r4 /* LSW = MSW >> r4 */<br>
+ l.j out /* go out */<br>
+ l.addi r3,r0,0x0 /* MSW = 0 */<br>
diff --git a/arch/openrisc/lib/muldi3.S b/arch/openrisc/lib/muldi3.S<br>
new file mode 100644<br>
index 0000000..902338a<br>
--- /dev/null<br>
+++ b/arch/openrisc/lib/muldi3.S<br>
@@ -0,0 +1,58 @@<br>
+/*<br>
+ * (C) Copyright 2011 - Franck JULLIEN <<a href="mailto:elec4fun@gmail.com">elec4fun@gmail.com</a>><br>
+ *<br>
+ * Extracted from gcc generated assembly.<br>
+ *<br>
+ * Multiply two quads. Hereafter, the illustration of what is going on :<br>
+ *<br>
+ * | r3 | r4 |<br>
+ * | r5 | r6 |<br>
+ * --------------------<br>
+ * | r4 * r6 |<br>
+ * | r3 * r6 | | +<br>
+ * | r5 * r4 | | +<br>
+ * | r3 * r5 | | | +<br>
+ * ------------------------------------------- =<br>
+ * | 64 bits result |<br>
+ *<br>
+ */<br>
+<br>
+.globl __muldi3<br>
+<br>
+__muldi3:<br>
+ /* starts with the full 64 bits mul (r4 * r6) */<br>
+ l.andi r7,r4,0xffff<br>
+ l.srli r8,r4,0x10<br>
+<br>
+ l.andi r11,r6,0xffff<br>
+ l.srli r12,r6,0x10<br>
+<br>
+ l.mul r13,r11,r7<br>
+ l.mul r11,r11,r8<br>
+ l.mul r7,r12,r7<br>
+<br>
+ l.srli r15,r13,0x10<br>
+ l.add r7,r7,r15<br>
+ l.add r7,r11,r7<br>
+ l.sfleu r11,r7<br>
+ <a href="http://l.bf" target="_blank">l.bf</a> no_carry<br>
+ l.mul r8,r12,r8<br>
+<br>
+ l.movhi r15,0x1<br>
+ l.add r8,r8,r15<br>
+<br>
+no_carry:<br>
+ /* Now compute r3 * r6 */<br>
+ l.mul r6,r6,r3<br>
+ /* and r4 * r5 */<br>
+ l.mul r4,r4,r5<br>
+ /* finaly previous results and put the result in r11:r12 */<br>
+ l.srli r3,r7,0x10<br>
+ l.slli r7,r7,0x10<br>
+ l.andi r13,r13,0xffff<br>
+ l.add r8,r8,r3<br>
+ l.add r11,r4,r6<br>
+ l.add r12,r7,r13<br>
+ l.add r11,r11,r8<br>
+ l.jr r9<br>
+ l.nop<br>
<span class="HOEnZb"><font color="#888888">--<br>
1.7.7<br>
<br>
</font></span></blockquote></div><br><div>ping</div>