Hi Sascha,<br> >> You have to adjust the TEXT_BASE in arch/arm/mach-imx/Kconfig so that the<br>
resulting link address is is your address space. <br><br> I have changed the TEXT_BASE to 0xA1F000000. Now it is pointing to 31st MB of 1st chip select. I did not understand what do you mean by " <span style="color: rgb(51, 102, 255);">resulting link address is your address space " ?</span><br>
<br>According to TEXT_BASE at 0xA1F000000, i have following stack and malloc area's<br><br> Malloc space: 0xa1900000 -> 0xa1f00000 (size 6 MB)<br> Stack space : 0xa18f8000 -> 0xa1900000 (size 32 kB)<br>
<br> >> For Linux you have to adjust the device size of the device which is passed to armlinux_add_dram() to 64MB.<br><br> I am adding two device using armlinux_add_dram() each with 32MB size and map_base address of 0xA0000000 and 0xB0000000 respectively.. <span style="color: rgb(51, 51, 255);">Is that fine or Can I have one device registered with map_base address of 0xA0000000 and 64MB size??</span><br>
<br>I have enabled MMU in barebox. There also i have a change for arm_create_section(). Following is section of code i have in pcm038_mmu_init()<br><br><i>static void pcm038_mmu_init(void)<br>{<br> mmu_init();<br><br>
arm_create_section(0xa0000000, 0xa0000000, 32, PMD_SECT_DEF_CACHED);<br> arm_create_section(0xb0000000, 0xa0000000, 32, PMD_SECT_DEF_UNCACHED);<br><br><br> setup_dma_coherent(0x10000000);<br><br>#if TEXT_BASE & (0x100000 - 1)<br>
#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary<br>#else<br> arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);<br>#endif<br> mmu_enable();<br>}</i><br><br>With all these changes, I see ping command hangs.. :(<br>
<br> If I replace the macro from PMD_SECT_DEF_UNCACHED to PMD_SECT_DEF_CACHED in the function pcm038_mmu_init(), the ping command throws some transmission timeout messages and exits saying the the destination is not Alive.<br>
<br>It would be great if you can help me out!!<br><br>Thanks,<br>Kuldeep.<br><br><div class="gmail_quote">On Mon, Aug 16, 2010 at 2:43 PM, Sascha Hauer <span dir="ltr"><<a href="mailto:s.hauer@pengutronix.de">s.hauer@pengutronix.de</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"><br>
Hi,<br>
<div><div></div><div class="h5"><br>
On Fri, Aug 13, 2010 at 08:47:38PM +0530, kuldeep ghan wrote:<br>
> Hi,<br>
> I am using PCM038 based custom board with changes in Memory<br>
> configuration. I want to know what all changes i have to do in barebox<br>
> source if I am reducing the size of DDR to 64 MB.<br>
> I have two 32MB DDR chips interfaced on CSD0 and CSD1. I am able to boot the<br>
> board with changes in pcm038 and lowlevel_init.S. I see that both the DDRs<br>
> are initialized properly and able to write and read to DDR address space.<br>
> Ping to command is failing with these changes. And I am not sure<br>
> about the changes required for stack size and malloc size.<br>
<br>
</div></div>You have to adjust the TEXT_BASE in arch/arm/mach-imx/Kconfig so that the<br>
resulting link address is is your address space. This should be<br>
sufficient for barebox. For Linux you have to adjust the device size of<br>
the device which is passed to armlinux_add_dram() to 64MB.<br>
<br>
I hope this helps<br>
<br>
Sascha<br>
<font color="#888888"><br>
<br>
--<br>
Pengutronix e.K. | |<br>
Industrial Linux Solutions | <a href="http://www.pengutronix.de/" target="_blank">http://www.pengutronix.de/</a> |<br>
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |<br>
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |<br>
</font></blockquote></div><br>