[PATCH 0/4] arm: socfpga: iossm: cleanup and fix SDRAM setup

[Michael Tretter]

barebox needs to wait for PLL lock before starting the SDRAM calibration
in the EMIF.

A developer can configure the PLLs that are used for the EMIF at device
configuration time. The SDM firmware writes the configured PLLs into the
handoff data.

Up until now, barebox always waited for the EMIF instance 0 PLL A, which
is likely to be the configured PLL, but actually barebox should wait for
the actually configured PLL.

Patches 1-3 are preparatory cleanup for Patch 4, which actually reads
the configuration from the handoff data and fixes the poll for the PLL
lock.

Signed-off-by: Michael Tretter <m.tretter at pengutronix.de>
---
Michael Tretter (4):
      arm: socfpga: iossm: remove unused num_port
      arm: socfpga: iossm: fix macro
      arm: socfpga: iossm: refactor register access
      arm: socfpga: iossm: wait for PLL lock from handoff table

 arch/arm/mach-socfpga/agilex5-sdram.c | 11 +++---
 arch/arm/mach-socfpga/iossm_mailbox.c | 72 ++++++++++++++++++++++++-----------
 arch/arm/mach-socfpga/iossm_mailbox.h |  4 +-
 3 files changed, 58 insertions(+), 29 deletions(-)
---
base-commit: a59cb95e1133c7f4844c68398c570694d1c7d9ed
change-id: 20260903-socfpga-fix-sdram-setup-60c41664791e

Best regards,
-- 
Michael Tretter <m.tretter at pengutronix.de>