[PATCH 2/2] arm: socfpga: axe5-eagle: drop hard-coded PHY reset in board code

[Michael Tretter]

Since GPIOLIB is now enabled for Agilex 5, the Ethernet driver resets
the Ethernet phy via the GPIO.

Remove the hard-coded reset code from the Arrow AXE5 board code.

Signed-off-by: Michael Tretter <m.tretter at pengutronix.de>
---
 arch/arm/boards/arrow-axe5-eagle/board.c | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/arch/arm/boards/arrow-axe5-eagle/board.c b/arch/arm/boards/arrow-axe5-eagle/board.c
index b197367f45e4..1ce48385f80d 100644
--- a/arch/arm/boards/arrow-axe5-eagle/board.c
+++ b/arch/arm/boards/arrow-axe5-eagle/board.c
@@ -3,33 +3,9 @@
 #include <init.h>
 #include <io.h>
 #include <bbu.h>
-#include <mach/socfpga/soc64-regs.h>
-
-static void axe5_ethernet_phy_reset(void)
-{
-	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x224);
-	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x228);
-	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x23c);
-	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x234);
-	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x248);
-	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x24c);
-
-	writel(0x410, 0x10c03304);
-	writel(0x410, 0x10c03300);
-	/*
-	 * reset the phy via GPIO10. We currently haven't got enough space
-	 * to enable the gpio driver in barebox.
-	 */
-	writel(0x000, 0x10c03300);
-	/* FIXME:  can this be decreased? */
-	mdelay(1000);
-	writel(0x410, 0x10c03300);
-}
 
 static int axe5_probe(struct device *dev)
 {
-	axe5_ethernet_phy_reset();
-
 	return 0;
 }
 

-- 
2.47.3