[PATCH master 1/5] clk: imx: pll14xx: enable PLL output in clk_pll1416x_early_set_rate()

[Ahmad Fatoum]

While clk_pll1416x_early_set_rate() programs the dividers, waits for
the lock and clears the bypass, it doesn't actually ungate the clock.

Therefore, the i.MX8M early clock init sets the CLKE bit by hand
afterwards, but it does so only for the ARM PLL.
SYS_PLL3 is reconfigured without CLKE being touched, because it works
out, because it's set at reset and BootROM doesn't clear it.

U-Boot's intpll_configure() sets CLKE at the end instead. As we are
going to align the early init with U-Boot for easier comparison in
future, let's rename our function to clk_pll1416x_early_configure() and
have it also ungate the clock.

Signed-off-by: Ahmad Fatoum <a.fatoum at pengutronix.de>
---
 arch/arm/mach-imx/imx8m.c     | 11 ++++-------
 drivers/clk/imx/clk-pll14xx.c | 14 +++++++++++---
 include/soc/imx8m/clk-early.h |  4 ++--
 3 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index 6286ab7344bc..3b2833a07ec2 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -116,8 +116,8 @@ static void __imx8m_early_clock_init(int cpu_type)
 		pll3_freq = 750000000UL;
 
 	/* Configure SYS_PLL3 */
-	clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL,
-				    pll3_freq, 25000000UL);
+	clk_pll1416x_early_configure(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL,
+				     pll3_freq, 25000000UL);
 
 	if (cpu_type == IMX_CPU_IMX8MP) {
 		/* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */
@@ -131,11 +131,8 @@ static void __imx8m_early_clock_init(int cpu_type)
 			IMX8M_CCM_TARGET_ROOTn_MUX(2));
 
 	/* Configure ARM PLL to 1.2GHz */
-	clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL,
-				    1200000000UL, 25000000UL);
-
-	clrsetbits_le32(ana + IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL, 0,
-			INTPLL_CLKE_MASK);
+	clk_pll1416x_early_configure(ana + IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL,
+				     1200000000UL, 25000000UL);
 
 	clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT),
 			IMX8M_CCM_TARGET_ROOTn_MUX(7),
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index 8a773f19f807..a0213c60516d 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -238,8 +238,8 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
 	return 0;
 }
 
-int clk_pll1416x_early_set_rate(void __iomem *base, unsigned long drate,
-			  unsigned long prate)
+int clk_pll1416x_early_configure(void __iomem *base, unsigned long drate,
+				 unsigned long prate)
 {
 	struct clk_pll14xx pll = {
 		.hw.clk = {
@@ -249,8 +249,16 @@ int clk_pll1416x_early_set_rate(void __iomem *base, unsigned long drate,
 		.rate_table = imx_pll1416x_tbl,
 		.rate_count = ARRAY_SIZE(imx_pll1416x_tbl),
 	};
+	int ret;
 
-	return clk_pll1416x_set_rate(&pll.hw, drate, prate);
+	ret = clk_pll1416x_set_rate(&pll.hw, drate, prate);
+	if (ret)
+		return ret;
+
+	/* enable the PLL output */
+	setbits_le32(base + GNRL_CTL, CLKE_MASK);
+
+	return 0;
 }
 
 static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
diff --git a/include/soc/imx8m/clk-early.h b/include/soc/imx8m/clk-early.h
index c2034e54f070..2430521d7a2e 100644
--- a/include/soc/imx8m/clk-early.h
+++ b/include/soc/imx8m/clk-early.h
@@ -3,7 +3,7 @@
 #ifndef __SOC_IMX8M_CLK_EARLY_H
 #define __SOC_IMX8M_CLK_EARLY_H
 
-int clk_pll1416x_early_set_rate(void __iomem *base, unsigned long drate,
-			  unsigned long prate);
+int clk_pll1416x_early_configure(void __iomem *base, unsigned long drate,
+				 unsigned long prate);
 
 #endif /* __SOC_IMX8M_CLK_EARLY_H */
-- 
2.47.3