[PATCH v4 0/4] ARM: i.MX8: add DDRC-ECC support

[Sascha Hauer]

On Mon, 16 Mar 2026 09:14:30 +0100, Steffen Trumtrar wrote:
> The i.MX8 DDRC controller supports using inline ECC with the DDR RAM.
> Inline ECC reduces the usable RAM size by 1/8: 7/8 RAM is for data and
> 1/8 RAM is for the ECC bits. Also, measuring random memory writes in
> linux with
> 
>     stress-ng --memthrash 4 --memthrash-method chunk1 -t 1m --metrics
> 
> [...]

Applied, thanks!

[1/4] ARM: i.MX: esdctl: fix spelling of ad(d)ress
      https://git.pengutronix.de/cgit/barebox/commit/?id=0826f8905b78 (link may not be stable)
[2/4] arm: mach-imx: esdctl.c: Add support for imx8mp inline ECC
      https://git.pengutronix.de/cgit/barebox/commit/?id=0651254b9450 (link may not be stable)
[3/4] drivers: ddr: imx8m: ddr_init.c: support ECC scrubbing
      https://git.pengutronix.de/cgit/barebox/commit/?id=101fcf16adf7 (link may not be stable)
[4/4] arm: boards: protonic-imx8ml: Add ECC + scrubbing
      https://git.pengutronix.de/cgit/barebox/commit/?id=d8361ee96223 (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer at pengutronix.de>