[PATCH v2 0/4] ARM: i.MX8: add DDRC-ECC support
Steffen Trumtrar
s.trumtrar at pengutronix.de
Mon Mar 9 00:46:12 PDT 2026
The i.MX8 DDRC controller supports using inline ECC with the DDR RAM.
Inline ECC reduces the usable RAM size by 1/8: 7/8 RAM is for data and
1/8 RAM is for the ECC bits. Also, measuring random memory writes in
linux with
stress-ng --memthrash 4 --memthrash-method chunk1 -t 1m --metrics
shows a performance decrease by ~10%.
If a board wants to support ECC, the lpddr4 RAM settings in the
according lpddr4-timing-* must be adapted to enable and configure the
ECC registers.
Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
---
Changes in v2:
- prt8ml: move ram timings to header
- prt8ml: build two images: with and without ecc
- add RAM size and scrubbing function to generic code
- Link to v1: https://lore.barebox.org/20260304-v2026-02-0-topic-imx8-ecc-v1-0-700698530c5c@pengutronix.de
---
David Jander (3):
arm: mach-imx: esdctl.c: Add support for imx8mp inline ECC
drivers: ddr: imx8m: ddr_init.c: support ECC scrubbing
arm: boards: protonic-imx8ml: Add ECC + scrubbing
Steffen Trumtrar (1):
ARM: i.MX: esdctl: fix spelling of ad(d)ress
arch/arm/boards/protonic-imx8m/Makefile | 2 +-
arch/arm/boards/protonic-imx8m/lowlevel-prt8ml.c | 21 +-
.../protonic-imx8m/lpddr4-timing-prt8ml-ecc.c | 26 +
.../boards/protonic-imx8m/lpddr4-timing-prt8ml.c | 1100 +------------------
.../boards/protonic-imx8m/lpddr4-timing-prt8ml.h | 1123 ++++++++++++++++++++
arch/arm/dts/imx8mp-prt8ml.dts | 10 +-
arch/arm/mach-imx/Kconfig | 9 +
arch/arm/mach-imx/esdctl.c | 91 +-
drivers/ddr/imx/imx8m_ddr_init.c | 95 ++
images/Makefile.imx | 2 +
include/soc/imx/ddr.h | 1 +
include/soc/imx8m/ddr.h | 4 +
12 files changed, 1370 insertions(+), 1114 deletions(-)
---
base-commit: f4122cb473bf8ca2d3d84cf7cd3c981d1da3309f
change-id: 20260304-v2026-02-0-topic-imx8-ecc-9206fee1f037
Best regards,
--
Steffen Trumtrar <s.trumtrar at pengutronix.de>
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