[PATCH 2/3] arm: socfpga: get rid of UART address for low-level debug

[Michael Tretter]

There are existing address definitions for UART0 and UART1 on SoCFPGA.
Having the UART address in the config is error prone.

Change it to debug ports, which allow to select the UART instead of
setting the address. While at it, simplify the configuration.

Signed-off-by: Michael Tretter <m.tretter at pengutronix.de>
---
 common/Kconfig.debug_ll         | 44 +++++++++++------------------------------
 include/mach/socfpga/debug_ll.h |  9 +++++++--
 2 files changed, 18 insertions(+), 35 deletions(-)

diff --git a/common/Kconfig.debug_ll b/common/Kconfig.debug_ll
index 3f06e2eef418..650bfe56383e 100644
--- a/common/Kconfig.debug_ll
+++ b/common/Kconfig.debug_ll
@@ -238,33 +238,12 @@ config DEBUG_ROCKCHIP_RK3399_UART
 	  Say Y here if you want kernel low-level debugging support
 	  on RK3399.
 
-config DEBUG_SOCFPGA_UART0
-	bool "Use SOCFPGA UART0 for low-level debug"
+config DEBUG_SOCFPGA_UART
+	bool "SoCFPGA Debug UART"
 	depends on ARCH_SOCFPGA
 	help
 	  Say Y here if you want kernel low-level debugging support
-	  on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
-
-config DEBUG_SOCFPGA_UART1
-	bool "Use SOCFPGA UART1 for low-level debug"
-	depends on ARCH_SOCFPGA
-	help
-	  Say Y here if you want kernel low-level debugging support
-	  on SOCFPGA(Arria 10) based platforms.
-
-config DEBUG_SOCFPGA_AGILEX5_UART0
-	bool "Use Agilex5 UART0 for low-level debug"
-	depends on ARCH_SOCFPGA_AGILEX5
-	help
-	  Say Y here if you want kernel low-level debugging support
-	  on Agilex5 based platforms.
-
-config DEBUG_SOCFPGA_AGILEX5_UART1
-	bool "Use Agilex5 UART1 for low-level debug"
-	depends on ARCH_SOCFPGA_AGILEX5
-	help
-	  Say Y here if you want kernel low-level debugging support
-	  on Agilex5 based platforms.
+	  on SoCFPGA based platforms.
 
 config DEBUG_STM32MP_UART
 	bool "Use STM32MP UART4 for low-level debug"
@@ -482,19 +461,18 @@ config DEBUG_ROCKCHIP_UART_PORT
 	  Choose UART port on which kernel low-level debug messages
 	  should be output.
 
-config DEBUG_SOCFPGA_UART_PHYS_ADDR
-	hex "Physical base address of debug UART" if DEBUG_LL
-	default 0xffc02000 if DEBUG_SOCFPGA_UART0
-	default 0xffc02100 if DEBUG_SOCFPGA_UART1
-	default 0x10c02000 if DEBUG_SOCFPGA_AGILEX5_UART0
-	default 0x10c02100 if DEBUG_SOCFPGA_AGILEX5_UART1
+config DEBUG_SOCFPGA_UART_PORT
+	int "SocFPGA UART debug port" if DEBUG_SOCFPGA_UART
+	default 0 if ARCH_SOCFPGA_CYCLONE5 || ARCH_SOCFPGA_AGILEX5
+	default 1 if ARCH_SOCFPGA_ARRIA10
 	depends on ARCH_SOCFPGA
+	help
+	  Select UART port used for early debugging.
 
 config DEBUG_SOCFPGA_UART_CLOCK
-	int "SoCFPGA UART debug clock" if DEBUG_LL
-	default 100000000 if ARCH_SOCFPGA_CYCLONE5
+	int "SoCFPGA UART debug clock" if DEBUG_SOCFPGA_UART
+	default 100000000 if ARCH_SOCFPGA_CYCLONE5 || ARCH_SOCFPGA_AGILEX5
 	default  50000000 if ARCH_SOCFPGA_ARRIA10
-	default 100000000 if ARCH_SOCFPGA_AGILEX5
 	depends on ARCH_SOCFPGA
 	help
 	  Choose UART root clock.
diff --git a/include/mach/socfpga/debug_ll.h b/include/mach/socfpga/debug_ll.h
index 86f6256af995..3d69d87545c1 100644
--- a/include/mach/socfpga/debug_ll.h
+++ b/include/mach/socfpga/debug_ll.h
@@ -4,9 +4,14 @@
 #define   __MACH_SOCFPGA_DEBUG_LL_H__
 
 #include <io.h>
+#include <mach/socfpga/soc64-regs.h>
 
-#ifdef CONFIG_DEBUG_LL
-#define UART_BASE	CONFIG_DEBUG_SOCFPGA_UART_PHYS_ADDR
+#define __SOCFPGA_UART_BASE(num)	SOCFPGA_UART##num##_ADDRESS
+#define SOCFPGA_UART_BASE(num)		__SOCFPGA_UART_BASE(num)
+
+#ifdef CONFIG_DEBUG_SOCFPGA_UART
+
+#define UART_BASE			SOCFPGA_UART_BASE(CONFIG_DEBUG_SOCFPGA_UART_PORT)
 
 #if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5)
 static inline uint8_t debug_ll_read_reg(void __iomem *base, int reg)

-- 
2.47.3