[PATCH 16/31] dma: ti: k3-udma-common: Update common code for AM62L DMAs
Sascha Hauer
s.hauer at pengutronix.de
Wed May 28 04:45:28 PDT 2025
Based on U-Boot downstream commit:
| commit 8679e1f2f3cb8de0b71e72e7538f5404f7abbd2b
| Author: Vignesh Raghavendra <vigneshr at ti.com>
| Date: Wed Feb 26 19:55:45 2025 +0530
|
| PENDING: dma: ti: k3-udma-common: Update common code for AM62L DMAs
|
| AM62L has a autopair mechanism to pair DMA and remote endpoints, and
| setup all the peer registers. So avoid accessing or setting up PEER
| registers for AM62L DMAs.
|
| Signed-off-by: Vignesh Raghavendra <vigneshr at ti.com>
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
drivers/dma/ti/k3-udma-common.c | 80 +++++++++++++++++++++++++++++------------
drivers/dma/ti/k3-udma-hwdef.h | 7 ++++
2 files changed, 64 insertions(+), 23 deletions(-)
diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-common.c
index d2ef9cc7b83d7fe4c2845b78b05c3a0e640cc589..8661d148aa1324828a168edb5caa496bb7e6da45 100644
--- a/drivers/dma/ti/k3-udma-common.c
+++ b/drivers/dma/ti/k3-udma-common.c
@@ -211,20 +211,24 @@ int udma_start(struct udma_chan *uc)
dev_dbg(uc->ud->dev, "%s: chan:%d dir:%s\n",
__func__, uc->id, udma_get_dir_text(uc->config.dir));
- /* Make sure that we clear the teardown bit, if it is set */
- udma_stop_hard(uc);
- /* Reset all counters */
- udma_reset_counters(uc);
+ if (uc->ud->match_data->type < DMA_TYPE_BCDMA_V2) {
+ /* Make sure that we clear the teardown bit, if it is set */
+ udma_stop_hard(uc);
+ /* Reset all counters */
+ udma_reset_counters(uc);
+ }
switch (uc->config.dir) {
case DMA_DEV_TO_MEM:
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
+ udma_rchanrt_update_bits(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN,
+ UDMA_CHAN_RT_CTL_EN);
/* Enable remote */
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
+ if (uc->ud->match_data->type < DMA_TYPE_BCDMA_V2)
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
dev_dbg(uc->ud->dev, "%s(rx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
__func__,
@@ -235,11 +239,13 @@ int udma_start(struct udma_chan *uc)
break;
case DMA_MEM_TO_DEV:
/* Enable remote */
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
+ if (uc->ud->match_data->type < DMA_TYPE_BCDMA_V2)
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
+ udma_tchanrt_update_bits(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN,
+ UDMA_CHAN_RT_CTL_EN);
dev_dbg(uc->ud->dev, "%s(tx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
__func__,
@@ -269,9 +275,17 @@ void udma_stop_mem2dev(struct udma_chan *uc, bool sync)
int i = 0;
u32 val;
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN |
- UDMA_CHAN_RT_CTL_TDOWN);
+ if (uc->ud->match_data->type == DMA_TYPE_BCDMA_V2 ||
+ uc->ud->match_data->type == DMA_TYPE_PKTDMA_V2) {
+ udma_tchanrt_update_bits(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN |
+ UDMA_CHAN_RT_CTL_TDOWN,
+ UDMA_CHAN_RT_CTL_TDOWN);
+ } else {
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN |
+ UDMA_CHAN_RT_CTL_TDOWN);
+ }
val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
@@ -285,6 +299,12 @@ void udma_stop_mem2dev(struct udma_chan *uc, bool sync)
i++;
}
+ if (uc->ud->match_data->type == DMA_TYPE_BCDMA_V2 ||
+ uc->ud->match_data->type == DMA_TYPE_PKTDMA_V2) {
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, UDMA_CHAN_RT_CTL_PAIR_COMPLETE);
+ return;
+ }
+
val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG);
if (val & UDMA_PEER_RT_EN_ENABLE)
dev_dbg(uc->ud->dev, "%s: peer not stopped TIMEOUT !\n", __func__);
@@ -295,9 +315,15 @@ void udma_stop_dev2mem(struct udma_chan *uc, bool sync)
int i = 0;
u32 val;
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE |
- UDMA_PEER_RT_EN_TEARDOWN);
+ if (uc->ud->match_data->type == DMA_TYPE_BCDMA_V2 ||
+ uc->ud->match_data->type == DMA_TYPE_PKTDMA_V2)
+ udma_rchanrt_update_bits(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN);
+ else
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE |
+ UDMA_PEER_RT_EN_TEARDOWN);
val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
@@ -311,6 +337,10 @@ void udma_stop_dev2mem(struct udma_chan *uc, bool sync)
i++;
}
+ if (uc->ud->match_data->type == DMA_TYPE_BCDMA_V2 ||
+ uc->ud->match_data->type == DMA_TYPE_PKTDMA_V2)
+ return;
+
val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG);
if (val & UDMA_PEER_RT_EN_ENABLE)
dev_dbg(uc->ud->dev, "%s: peer not stopped TIMEOUT !\n", __func__);
@@ -625,7 +655,10 @@ int udma_alloc_rx_resources(struct udma_chan *uc)
}
rflow = uc->rflow;
- if (ud->tflow_cnt) {
+
+ if (ud->match_data->type >= DMA_TYPE_BCDMA_V2) {
+ fd_ring_id = rflow->id;
+ } else if (ud->tflow_cnt) {
fd_ring_id = ud->tflow_cnt + rflow->id;
} else {
fd_ring_id = ud->bchan_cnt + ud->tchan_cnt + ud->echan_cnt +
@@ -838,9 +871,10 @@ int bcdma_alloc_bchan_resources(struct udma_chan *uc)
if (ret)
return ret;
- ret = k3_ringacc_request_rings_pair(ud->ringacc, uc->bchan->id, -1,
- &uc->bchan->t_ring,
- &uc->bchan->tc_ring);
+ ret = k3_ringacc_request_rings_pair(ud->ringacc,
+ ud->match_data->chan_cnt + uc->bchan->id,
+ -1, &uc->bchan->t_ring,
+ &uc->bchan->tc_ring);
if (ret) {
ret = -EBUSY;
goto err_ring;
@@ -1064,7 +1098,7 @@ int udma_of_xlate(struct dma *dma, struct of_phandle_args *args)
ucc->notdpkt = ep_config->notdpkt;
ucc->ep_type = ep_config->ep_type;
- if (ud->match_data->type == DMA_TYPE_PKTDMA &&
+ if (ud->match_data->type >= DMA_TYPE_PKTDMA &&
ep_config->mapped_channel_id >= 0) {
ucc->mapped_channel_id = ep_config->mapped_channel_id;
ucc->default_flow_id = ep_config->default_flow_id;
diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h
index 3d6b4d10fff1156f5d0a0a8ae8d0c940b8060236..6fbbd88e75fc8ee737a36c9f573d99a4e0c77392 100644
--- a/drivers/dma/ti/k3-udma-hwdef.h
+++ b/drivers/dma/ti/k3-udma-hwdef.h
@@ -37,6 +37,8 @@
#define UDMA_RFLOW_REG(x) (UDMA_RFLOW_RF##x##_REG)
+#define UDMA_RX_FLOWRT_RFA 0x8
+
/* TX chan regs */
#define UDMA_TCHAN_TCFG_REG 0x0
#define UDMA_TCHAN_TCREDIT_REG 0x4
@@ -60,6 +62,7 @@
/* TX chan RT regs */
#define UDMA_TCHAN_RT_CTL_REG 0x0
+#define UDMA_TCHAN_RT_CFG_REG 0x4
#define UDMA_TCHAN_RT_SWTRIG_REG 0x8
#define UDMA_TCHAN_RT_STDATA_REG 0x80
@@ -79,6 +82,7 @@
/* RX chan RT regs */
#define UDMA_RCHAN_RT_CTL_REG 0x0
+#define UDMA_RCHAN_RT_CFG_REG 0x4
#define UDMA_RCHAN_RT_SWTRIG_REG 0x8
#define UDMA_RCHAN_RT_STDATA_REG 0x80
@@ -132,6 +136,9 @@
#define UDMA_CHAN_RT_CTL_TDOWN BIT(30)
#define UDMA_CHAN_RT_CTL_PAUSE BIT(29)
#define UDMA_CHAN_RT_CTL_FTDOWN BIT(28)
+#define UDMA_CHAN_RT_CTL_AUTOPAIR BIT(23)
+#define UDMA_CHAN_RT_CTL_PAIR_TIMEOUT BIT(17)
+#define UDMA_CHAN_RT_CTL_PAIR_COMPLETE BIT(16)
#define UDMA_CHAN_RT_CTL_ERROR BIT(0)
/* UDMA_TCHAN_RT_PEER_RT_EN_REG/UDMA_RCHAN_RT_PEER_RT_EN_REG (PSI-L: 0x408) */
--
2.39.5
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