[PATCH 22/22] watchdog: stm32_iwdg: bail out before zero division

[Ahmad Fatoum]

clang-analyzer reports that a zero division may be possible while
computing presc. This can only happen if the watchdog is driven by a
non-zero clock rate under 4096Hz. This won't happen in practice, but
clang-analyzer doesn't know that, so just add a check to silence it.

Signed-off-by: Ahmad Fatoum <a.fatoum at pengutronix.de>
---
 drivers/watchdog/stm32_iwdg.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/watchdog/stm32_iwdg.c b/drivers/watchdog/stm32_iwdg.c
index 6ac9e7d56e9e..c47a8cac15ec 100644
--- a/drivers/watchdog/stm32_iwdg.c
+++ b/drivers/watchdog/stm32_iwdg.c
@@ -62,6 +62,9 @@ static int stm32_iwdg_start(struct stm32_iwdg *wd, unsigned int timeout)
 
 	/* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
 	presc = roundup_pow_of_two(presc);
+	if (!presc)
+		return -ERANGE;
+
 	iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
 	iwdg_rlr = ((timeout * wd->rate) / presc) - 1;
 
-- 
2.39.5