[PATCH 08/14] ARM: mach-imx: tzasc: add imx6[q|ul]_tzc380_is_bypassed()

[Sascha Hauer]

On Fri, Jun 27, 2025 at 05:57:23PM +0200, Marco Felsch wrote:
> On 25-06-27, Sascha Hauer wrote:
> > From: Marco Felsch <m.felsch at pengutronix.de>
> > 
> > The TZASC_BYP bits in the IOMUX GPR offer a great way to shoot yourself
> > in the foot. These bits are cleared by default and with these bits
> > cleared the TZASC will never check DDR transactions. The TZASC can be
> > configured normally with the bits cleared, it just doesn't work and all
> > secure regions can be accessed by the normal worls. These
> > bits can only be set in the DCD table, trying to set them in code will
> > make the system hang. As the DCD tables are board specific it's easy to
> 
> I think this is not entirely true. At least the i.MX6 TRM says, that any
> DDR access must be done before the TZASC is turned on.
> 
> Since most i.MX6/7 boards do use the DCD RAM setup and tell the BootROM
> to load the barebox(-pbl) directly into RAM, we can enable it only from
> DCD. But it should still be possible to enable it within the code, like
> we do for i.MX8M. This only requires that the barebox-pbl is loaded into
> internal OCRAM which is the rare case for i.MX6/7 boards.

So you mean that the bypass bit has to be set before the DDR controller
is initialized which requires us to put it into the DCD table when we
initialize the DDR controller in DCD?

Well, that makes more sense to me. I'll adjust the commit message
accordingly.

Sascha

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