[PATCH 4/5] ARM: mach-imx: tzasc: add imx6q_tzc380_early_ns_region1()

[Ahmad Fatoum]

Hi,

On 6/24/25 12:55, Marco Felsch wrote:
> Hi Ahmad,
> 
> On 25-06-24, Ahmad Fatoum wrote:
>> Hello Marco,
>>
>> On 6/19/25 17:25, Marco Felsch wrote:
>>> +void imx6q_tzc380_early_ns_region1(void)
>>> +{
>>> +	resource_size_t ram_sz = imx6_get_mmdc_sdram_size();
>>> +
>>> +	imx_tzc380_init_and_setup(IOMEM(MX6_TZASC1_BASE), 1,
>>> +				  MX6_MMDC_PORT01_BASE_ADDR, ram_sz,
>>> +				  TZC380_REGION_SP_NS_RW);
>>> +	imx_tzc380_init_and_setup(IOMEM(MX6_TZASC2_BASE), 1,
>>> +				  MX6_MMDC_PORT01_BASE_ADDR, ram_sz,
>>> +				  TZC380_REGION_SP_NS_RW);
>>
>> What's the point of having two TZASC's if you configure them the exact
>> same way..?
> 
> The i.MX6QDL do have two MMDCs. Depending on the system/board-design the
> controllers support interleaved access. I'm not that deep into that
> topic but I think this was mostly used by LPDDR2 setups. For DDR3 setups
> only one MMDC can be used.

Mhm, it still looks strange to configure the same into both instead of
the actual physical address space mappings they have, but given that the
physical address is used to route the transfer in the first place, I
guess it doesn't matter and the way it's written now is simpler.

Acked-by: Ahmad Fatoum <a.fatoum at pengutronix.de>

Cheers,
Ahmad

> 
> Regards,
>   Marco
> 
>>> +}
>>> +
>>>  void imx8m_tzc380_init(void)
>>>  {
>>>  	u32 __iomem *gpr = IOMEM(MX8M_IOMUXC_GPR_BASE_ADDR);
>>> diff --git a/include/mach/imx/tzasc.h b/include/mach/imx/tzasc.h
>>> index 51c86f168ee4..4d3f26fc82f1 100644
>>> --- a/include/mach/imx/tzasc.h
>>> +++ b/include/mach/imx/tzasc.h
>>> @@ -6,6 +6,7 @@
>>>  #include <linux/types.h>
>>>  #include <asm/system.h>
>>>  
>>> +void imx6q_tzc380_early_ns_region1(void);
>>>  void imx8m_tzc380_init(void);
>>>  bool imx8m_tzc380_is_enabled(void);
>>>  
>>
>> -- 
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>>
>>
> 

-- 
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Steuerwalder Str. 21              | http://www.pengutronix.de/  |
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