[PATCH 1/3] ppc: implement sync_caches_for_execution

[Ahmad Fatoum]

Instead of opencoding flush_dcache followed by invalidate_icache,
implement sync_caches_for_execution().

Signed-off-by: Ahmad Fatoum <a.fatoum at barebox.org>
---
 arch/powerpc/boards/freescale-p1010rdb/p1010rdb.c | 3 +--
 arch/powerpc/boards/freescale-p1022ds/p1022ds.c   | 3 +--
 arch/powerpc/boards/freescale-p2020rdb/p2020rdb.c | 3 +--
 arch/powerpc/boards/owc-da923rc/da923rc.c         | 3 +--
 arch/powerpc/cpu-85xx/Makefile                    | 1 +
 arch/powerpc/cpu-85xx/cache.c                     | 9 +++++++++
 arch/powerpc/cpu-85xx/mmu.c                       | 6 ++----
 arch/powerpc/include/asm/cache.h                  | 2 ++
 8 files changed, 18 insertions(+), 12 deletions(-)
 create mode 100644 arch/powerpc/cpu-85xx/cache.c

diff --git a/arch/powerpc/boards/freescale-p1010rdb/p1010rdb.c b/arch/powerpc/boards/freescale-p1010rdb/p1010rdb.c
index c8f19bf2c147..023fb32bf3b1 100644
--- a/arch/powerpc/boards/freescale-p1010rdb/p1010rdb.c
+++ b/arch/powerpc/boards/freescale-p1010rdb/p1010rdb.c
@@ -164,8 +164,7 @@ static int p1010rdb_board_init_r(void)
 	const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1);
 
 	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
+	sync_caches_for_execution();
 
 	/* invalidate existing TLB entry for flash */
 	e500_disable_tlb(flash_esel);
diff --git a/arch/powerpc/boards/freescale-p1022ds/p1022ds.c b/arch/powerpc/boards/freescale-p1022ds/p1022ds.c
index f46a0a20aee0..e3591454f831 100644
--- a/arch/powerpc/boards/freescale-p1022ds/p1022ds.c
+++ b/arch/powerpc/boards/freescale-p1022ds/p1022ds.c
@@ -165,8 +165,7 @@ static int p1022ds_board_init_r(void)
 	fsl_set_lbc_or(1, 0xffff8796);
 
 	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
+	sync_caches_for_execution();
 
 	/* invalidate existing TLB entry for flash */
 	e500_disable_tlb(flash_esel);
diff --git a/arch/powerpc/boards/freescale-p2020rdb/p2020rdb.c b/arch/powerpc/boards/freescale-p2020rdb/p2020rdb.c
index b1efee26f11e..ba4f58be10e7 100644
--- a/arch/powerpc/boards/freescale-p2020rdb/p2020rdb.c
+++ b/arch/powerpc/boards/freescale-p2020rdb/p2020rdb.c
@@ -246,8 +246,7 @@ static int board_init_r(void)
 	fsl_set_lbc_or(0, 0xff000ff7);
 
 	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
+	sync_caches_for_execution();
 
 	/* invalidate existing TLB entry for flash */
 	e500_disable_tlb(flash_esel);
diff --git a/arch/powerpc/boards/owc-da923rc/da923rc.c b/arch/powerpc/boards/owc-da923rc/da923rc.c
index b3e347794b49..baede439b15b 100644
--- a/arch/powerpc/boards/owc-da923rc/da923rc.c
+++ b/arch/powerpc/boards/owc-da923rc/da923rc.c
@@ -147,8 +147,7 @@ static int da923rc_board_init_r(void)
 
 	da923rc_boardinfo_get(&binfo);
 
-	flush_dcache();
-	invalidate_icache();
+	sync_caches_for_execution();
 
 	/* Clear LBC error interrupts */
 	out_be32(lbc + FSL_LBC_LTESR_OFFSET, 0xffffffff);
diff --git a/arch/powerpc/cpu-85xx/Makefile b/arch/powerpc/cpu-85xx/Makefile
index c7c5c8a00663..cc85eb759472 100644
--- a/arch/powerpc/cpu-85xx/Makefile
+++ b/arch/powerpc/cpu-85xx/Makefile
@@ -2,6 +2,7 @@
 
 obj-y			+= traps.o
 obj-y			+= tlb.o
+obj-y			+= cache.o
 obj-$(CONFIG_MMU)	+= mmu.o
 extra-y			+= start.o
 extra-y			+= resetvec.o
diff --git a/arch/powerpc/cpu-85xx/cache.c b/arch/powerpc/cpu-85xx/cache.c
new file mode 100644
index 000000000000..fcd71b6f9b76
--- /dev/null
+++ b/arch/powerpc/cpu-85xx/cache.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <asm/cache.h>
+
+void sync_caches_for_execution(void)
+{
+	flush_dcache();
+	invalidate_icache();
+}
diff --git a/arch/powerpc/cpu-85xx/mmu.c b/arch/powerpc/cpu-85xx/mmu.c
index 3bd75281eb98..091873d966a3 100644
--- a/arch/powerpc/cpu-85xx/mmu.c
+++ b/arch/powerpc/cpu-85xx/mmu.c
@@ -47,10 +47,8 @@ int arch_remap_range(void *virt_addr, phys_addr_t phys_addr, size_t size, unsign
 			break;
 		e500_read_tlbcam_entry(esel, &valid, &tsize, &epn,
 				&rpn);
-		if (pte_flags & MAS2_I) {
-			flush_dcache();
-			invalidate_icache();
-		}
+		if (pte_flags & MAS2_I)
+			sync_caches_for_execution();
 		e500_set_tlb(1, epn, rpn, MAS3_SX|MAS3_SW|MAS3_SR,
 				(u8)wimge, 0, esel, tsize, 1);
 		/* convert tsize to bytes to increment address. */
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index c9066099ab6d..2edf11de2ef8 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -35,6 +35,8 @@ extern void clean_dcache_range(unsigned long start, unsigned long stop);
 extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
 extern void flush_dcache(void);
 extern void invalidate_icache(void);
+#define sync_caches_for_execution sync_caches_for_execution
+extern void sync_caches_for_execution(void);
 #ifdef CFG_INIT_RAM_LOCK
 extern void unlock_ram_in_cache(void);
 #endif /* CFG_INIT_RAM_LOCK */
-- 
2.39.5