[PATCH] ddr: imx9: fix DRAM PLL bypass

[Sascha Hauer]

On Fri, 18 Jul 2025 20:12:42 +0200, Mathieu Anquetin via B4 Relay wrote:
> On i.MX9, clock selection for DDR PHY is done by setting/clearing bit 0
> of GPR_SHARED2 register.
> 
> This is done using the generic function ccm_shared_gpr_set() which takes
> two arguments, the GPR number and the value to set. However, this
> function did not use the GPR number to calculate the offset of the
> GPR_SHAREDn register to set in the CCM.
> 
> [...]

Applied, thanks!

[1/1] ddr: imx9: fix DRAM PLL bypass
      https://git.pengutronix.de/cgit/barebox/commit/?id=a10fb28638ab (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer at pengutronix.de>