[PATCH] zedboard correct comments in lowlevel.c

[johannes at gnu-linux.rocks]

From: Johannes Roith <johannes at gnu-linux.rocks>

Signed-off-by: Johannes Roith <johannes at gnu-linux.rocks>

According to the TRM of the Zynq 7000 the registers under 'UART1 pinmux'
represents the pinmux for UART0. So, I fixed the comments and also
added the pin number for the UART0, UART1 and QSPI pins to the pinctrl.

Link to TRM page for pinmux:

https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Register-slcr-MIO_PIN_50

---
 arch/arm/boards/avnet-zedboard/lowlevel.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c
index 026a03d04b..605aab783a 100644
--- a/arch/arm/boards/avnet-zedboard/lowlevel.c
+++ b/arch/arm/boards/avnet-zedboard/lowlevel.c
@@ -223,12 +223,13 @@ static void avnet_zedboard_ps7_init(void)
 	writel(0x00000081, 0XF8006000);
 
 	/* poor mans pinctrl */
+	/* UART1 pinmux TxD: MIO_PIN 48, RxD: MIO_PIN 49 */
 	writel(0x000002E0, ZYNQ_MIO_BASE + 0xC0);
 	writel(0x000002E1, ZYNQ_MIO_BASE + 0xC4);
-	/* UART1 pinmux */
+	/* UART0 pinmux TxD: MIO_PIN 50, RxD: MIO_PIN 51 */
 	writel(0x000002E1, ZYNQ_MIO_BASE + 0xC8);
 	writel(0x000002E0, ZYNQ_MIO_BASE + 0xCC);
-	/* QSPI pinmux */
+	/* QSPI pinmux MIO_PIN 01 - 08 */
 	writel(0x00001602, ZYNQ_MIO_BASE + 0x04);
 	writel(0x00000702, ZYNQ_MIO_BASE + 0x08);
 	writel(0x00000702, ZYNQ_MIO_BASE + 0x0c);
-- 
2.39.5