RK3588 CPLL question

[Alexander Shiyan]

Hello.

Yes, this is the best option, but it is not possible yet. Any change in CPLL
frequency causes the system to freeze. I am still trying to figure this out.

Thanks!

пт, 4 апр. 2025 г. в 10:29, Sascha Hauer <s.hauer at pengutronix.de>:
>
> On Thu, Apr 03, 2025 at 05:20:33PM +0300, Alexander Shiyan wrote:
> > I found this hack:
> > https://github.com/u-boot/u-boot/blob/master/drivers/clk/rockchip/clk_rk3588.c#L1933
>
> Let's do the same then.
>
> It would be nicer to have the CPLL setting in the assigned-clock-rates
> property. That should be done in the upstream dtsi though, overwriting
> the assigned-clock-rates in the barebox dtsi would mean we would have to
> copy the many existing settings and hope they don't change upstream.
>
> Sascha
>
> >
> > чт, 3 апр. 2025 г. в 17:08, Sascha Hauer <s.hauer at pengutronix.de>:
> > >
> > > On Thu, Apr 03, 2025 at 05:01:05PM +0300, Alexander Shiyan wrote:
> > > > Thanks Sascha!
> > > >
> > > > So something is wrong here.
> > > > At least the GMAC0/1 interfaces end up with the wrong frequency.
> > > > I have another image with u-boot and Rockchip kernel where CPLL
> > > > is 1.5GHz and network is ok.
> > >
> > > The only place where the PLL rates are configured in barebox is via
> > > assigned-clock-rates in the clock controller node. PLL_CPLL doesn't show
> > > up there, so I would assume it is just left to the default whatever that
> > > is.
> > >
> > > You could chainload barebox from U-Boot and see what the CPLL rate is
> > > then.
> > >
> > > Sascha
> > >
> > > --
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> >
>
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