[PATCH v2 01/12] ARM: Layerscape: TQMLS1046a: Update DDR timings

[Sascha Hauer]

Update DDR timings from TQ U-Boot.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/tqmls1046a/lowlevel.c | 54 +++++++++++++++++------------------
 1 file changed, 27 insertions(+), 27 deletions(-)

diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 2551a18ec6..6d25b5cda8 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -38,43 +38,43 @@ static struct fsl_ddr_controller ddrc[] = {
 	.cs[3].config       = 0x00000000,
 	.cs[3].config_2     = 0x00000000,
 	.timing_cfg_3       = 0x020F1100,
-	.timing_cfg_0       = 0x77660008,
-	.timing_cfg_1       = 0xF1FCC265,
-	.timing_cfg_2       = 0x0059415E,
-	.ddr_sdram_cfg      = 0x65000000,
+	.timing_cfg_0       = 0xF7660008,
+	.timing_cfg_1       = 0xF1FC4178,
+	.timing_cfg_2       = 0x00590160,
+	.ddr_sdram_cfg      = 0x65000008,
 	.ddr_sdram_cfg_2    = 0x00401150,
-	.ddr_sdram_cfg_3    = 0x00000000,
-	.ddr_sdram_mode     = 0x03010625,
+	.ddr_sdram_cfg_3    = 0x40000000,
+	.ddr_sdram_mode     = 0x01030631,
 	.ddr_sdram_mode_2   = 0x00100200,
-	.ddr_sdram_mode_3   = 0x00010625,
-	.ddr_sdram_mode_4   = 0x00100200,
-	.ddr_sdram_mode_5   = 0x00010625,
-	.ddr_sdram_mode_6   = 0x00100200,
-	.ddr_sdram_mode_7   = 0x00010625,
-	.ddr_sdram_mode_8   = 0x00100200,
+	.ddr_sdram_mode_3   = 0x00000000,
+	.ddr_sdram_mode_4   = 0x00000000,
+	.ddr_sdram_mode_5   = 0x00000000,
+	.ddr_sdram_mode_6   = 0x00000000,
+	.ddr_sdram_mode_7   = 0x00000000,
+	.ddr_sdram_mode_8   = 0x00000000,
 	.ddr_sdram_mode_9   = 0x00000500,
-	.ddr_sdram_mode_10  = 0x04400000,
-	.ddr_sdram_mode_11  = 0x00000400,
-	.ddr_sdram_mode_12  = 0x04400000,
-	.ddr_sdram_mode_13  = 0x00000400,
-	.ddr_sdram_mode_14  = 0x04400000,
-	.ddr_sdram_mode_15  = 0x00000400,
-	.ddr_sdram_mode_16  = 0x04400000,
-	.ddr_sdram_interval = 0x0F3C0000,
+	.ddr_sdram_mode_10  = 0x08800000,
+	.ddr_sdram_mode_11  = 0x00000000,
+	.ddr_sdram_mode_12  = 0x00000000,
+	.ddr_sdram_mode_13  = 0x00000000,
+	.ddr_sdram_mode_14  = 0x00000000,
+	.ddr_sdram_mode_15  = 0x00000000,
+	.ddr_sdram_mode_16  = 0x00000000,
+	.ddr_sdram_interval = 0x0F3C079E,
 	.ddr_data_init      = 0xDEADBEEF,
-	.ddr_sdram_clk_cntl = 0x02000000,
+	.ddr_sdram_clk_cntl = 0x03000000,
 	.ddr_init_addr      = 0x00000000,
 	.ddr_init_ext_addr  = 0x00000000,
-	.timing_cfg_4       = 0x00224002,
-	.timing_cfg_5       = 0x04401400,
+	.timing_cfg_4       = 0x00220002,
+	.timing_cfg_5       = 0x00000000,
 	.timing_cfg_6       = 0x00000000,
 	.timing_cfg_7       = 0x25500000,
-	.timing_cfg_8       = 0x03335A00,
+	.timing_cfg_8       = 0x05447A00,
 	.timing_cfg_9       = 0x00000000,
 	.ddr_zq_cntl        = 0x8A090705,
-	.ddr_wrlvl_cntl     = 0x86550609,
-	.ddr_wrlvl_cntl_2   = 0x09080806,
-	.ddr_wrlvl_cntl_3   = 0x06040409,
+	.ddr_wrlvl_cntl     = 0x8605070A,
+	.ddr_wrlvl_cntl_2   = 0x0A080807,
+	.ddr_wrlvl_cntl_3   = 0x0706060A,
 	.ddr_sr_cntr        = 0x00000000,
 	.ddr_sdram_rcw_1    = 0x00000000,
 	.ddr_sdram_rcw_2    = 0x00000000,

-- 
2.39.5