[PATCH 05/12] mci: arasan: register sdcard/sampleclk

[Ahmad Fatoum]

On 08.03.24 12:17, Steffen Trumtrar wrote:
> +static unsigned long arasan_zynqmp_sampleclk_recalc_rate(struct clk_hw *hw,
> +							 unsigned long parent_rate)
> +{
> +	return 0;

In HS200 mode, Linux reports this as 200MHz. Returning zero here is confusing,
even if no one depends on it. What we should be doing, I think, is set

  host->actual_clock = host->clock

at the end of mci_set_ios() and return host->sdhci.mci->actual_clock here.

> +static unsigned long arasan_zynqmp_sdcardclk_recalc_rate(struct clk_hw *hw,
> +							 unsigned long parent_rate)
> +{
> +	return 0;
> +};

Same here

> +static int arasan_sdhci_register_sdclk(struct sdhci_arasan_clk_data *sdhci_arasan,
> +				       struct clk *clk_xin,
> +				       struct device *dev)
> +{
> +	struct device_node *np = dev->of_node;
> +	u32 num_clks = 0;
> +	int ret;
> +
> +	/* Providing a clock to the PHY is optional; no error if missing */
> +	if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
> +		return 0;
> +
> +	ret = arasan_sdhci_register_sdcardclk(sdhci_arasan, clk_xin, dev);
> +	if (ret)
> +		return ret;
> +
> +	if (num_clks) {
> +		ret = arasan_sdhci_register_sampleclk(sdhci_arasan, clk_xin,
> +						      dev);
		s/ret = /return/

While at it, you can drop the braces.


> +	}
> +
> +	return 0;
> +}
> +
>  /**
>   * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
>   *
> @@ -400,6 +703,8 @@ static int arasan_sdhci_probe(struct device *dev)
>  	mci->f_max = clk_get_rate(clk_xin);
>  	mci->f_min = 50000000 / 256;
>  
> +	arasan_sdhci_register_sdclk(&arasan_sdhci->clk_data, clk_xin, dev);
> +
>  	arasan_dt_parse_clk_phases(dev, &arasan_sdhci->clk_data);
>  
>  	/* parse board supported bus width capabilities */
> 

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