[PATCH master 3/4] fpga: socfpga-fpga2sdram-bridge: consult HANDOFF_FPGA2SDR register

[Ahmad Fatoum]

Previous commit started populating the handoff register, which the
Linux SoCFPA FPGA2SDRAM bridge driver would use to bring the correct
SDRAM ports on the bridge out of reset.

An alternative is skipping the Linux driver and doing setup in barebox.
So far, we just enabled all ports, but this can lead to discrepancy
between barebox and Linux if both drivers are enabled.

This is the case for the upstream Terasic DE10-Nano, which specifies a
mask of 0x1ff in its generated Quartus headers, which is narrower than
the maximum possible bitmask of 0x3fff.

Therefore, let's start using the handoff register in barebox as well.
At probe time, the register is currently only populated on Cyclone V SoCs,
so arria10 will just read a zero and fallback to the old behavior of writing
0x3fff.

Signed-off-by: Ahmad Fatoum <a.fatoum at pengutronix.de>
---
 drivers/fpga/socfpga-fpga2sdram-bridge.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/fpga/socfpga-fpga2sdram-bridge.c b/drivers/fpga/socfpga-fpga2sdram-bridge.c
index 202dfaa82b5e..961a083ae512 100644
--- a/drivers/fpga/socfpga-fpga2sdram-bridge.c
+++ b/drivers/fpga/socfpga-fpga2sdram-bridge.c
@@ -106,8 +106,11 @@ static int alt_fpga_bridge_probe(struct device *dev)
 	if (!priv)
 		return -ENOMEM;
 
-	/* enable all ports for now */
-	priv->mask = ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSK;
+	priv->mask = readl(SOCFPGA_SYSMGR_ADDR + SYSMGR_ISWGRP_HANDOFF3);
+	if (!priv->mask) {
+		/* enable all ports if we don't know better */
+		priv->mask = ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSK;
+	}
 
 	priv->dev = dev;
 
-- 
2.39.2