[PATCH v2 17/18] ARM: i.MX8M: cleanup MX8M*_ATF_BL33_BASE_ADDR defines

[Marco Felsch]

Instead of having three defines for the same just use the base
definition which is MX8M_ATF_BL33_BASE_ADDR and drop the others.

Signed-off-by: Marco Felsch <m.felsch at pengutronix.de>
---
 Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg | 10 +++++-----
 arch/arm/boards/phytec-som-imx8mq/lowlevel.c        |  2 +-
 arch/arm/boards/zii-imx8mq-dev/lowlevel.c           |  2 +-
 include/mach/imx/atf.h                              |  2 --
 4 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg b/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg
index cc0bec6b74b9..fa25348757af 100644
--- a/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg
+++ b/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg
@@ -71,15 +71,15 @@ proc ddr_init { } {
 
 proc start_barebox {} {
 	#
-	# We have to place our image at MX8MQ_ATF_BL33_BASE_ADDR in order
+	# We have to place our image at MX8M_ATF_BL33_BASE_ADDR in order
 	# to be able to initialize ATF firmware since that's where it
 	# expects entry point to BL33 would be
 	#
-	set MX8MQ_ATF_BL33_BASE_ADDR	0x40200000
+	set MX8M_ATF_BL33_BASE_ADDR	0x40200000
 	echo "Bootstrap: Loading Barebox"
-	load_image images/start_zii_imx8mq_dev.pblb $MX8MQ_ATF_BL33_BASE_ADDR bin
-	echo [format "Bootstrap: Jumping to 0x%08x" $MX8MQ_ATF_BL33_BASE_ADDR]
-	resume $MX8MQ_ATF_BL33_BASE_ADDR
+	load_image images/start_zii_imx8mq_dev.pblb $MX8M_ATF_BL33_BASE_ADDR bin
+	echo [format "Bootstrap: Jumping to 0x%08x" $MX8M_ATF_BL33_BASE_ADDR]
+	resume $MX8M_ATF_BL33_BASE_ADDR
 }
 
 proc board_init { } {
diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
index 5708c8d75484..362b3ed823c1 100644
--- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
@@ -88,7 +88,7 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void)
  *
  * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it
  *
- * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR,
+ * 5. BL31 exits EL3 into EL2 at address MX8M_ATF_BL33_BASE_ADDR,
  *    executing start_phytec_phycore_imx8mq() the third time
  *
  * 6. Standard barebox boot flow continues
diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
index 42cd05d3f17c..4184748cd858 100644
--- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
+++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
@@ -174,7 +174,7 @@ static __noreturn noinline void zii_imx8mq_dev_start(void)
  *
  * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it
  *
- * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR,
+ * 5. BL31 exits EL3 into EL2 at address MX8M_ATF_BL33_BASE_ADDR,
  *    executing start_nxp_imx8mq_evk() the third time
  *
  * 6. Standard barebox boot flow continues
diff --git a/include/mach/imx/atf.h b/include/mach/imx/atf.h
index fb367d6a7052..15bd13eb27cc 100644
--- a/include/mach/imx/atf.h
+++ b/include/mach/imx/atf.h
@@ -15,8 +15,6 @@
 #define MX8MP_ATF_BL31_BASE_ADDR	0x00970000
 #define MX8MQ_ATF_BL31_BASE_ADDR	0x00910000
 #define MX8M_ATF_BL33_BASE_ADDR		0x40200000
-#define MX8MM_ATF_BL33_BASE_ADDR	MX8M_ATF_BL33_BASE_ADDR
-#define MX8MQ_ATF_BL33_BASE_ADDR	MX8M_ATF_BL33_BASE_ADDR
 #define MX93_ATF_BL31_BASE_ADDR		0x204e0000
 #define MX93_ATF_BL33_BASE_ADDR		0x80200000
 
-- 
2.39.2