[PATCH 060/112] ARM: pbl: add 64K segment alignment for PE/COFF

[Sascha Hauer]

On Wed, Jan 03, 2024 at 07:12:20PM +0100, Ahmad Fatoum wrote:
> An EFI stubbed ARM64 kernel can be booted either via EFI or via the
> normal boot protocol. We'll want barebox to be able to behave the same,
> so extend section alignment to enable this.

This description reads as if it would change something, but at this
point this patch only introduces unused defines. They are first used in
086/112.

Does it hurt to move the usage of PBL_SEGMENT_ALIGN and PECOFF_EDATA_PADDING
to this patch? If not, I'd suggest doing so to make the intention of
this patch clearer.

Sascha

> 
> Signed-off-by: Ahmad Fatoum <a.fatoum at pengutronix.de>
> ---
>  arch/arm/include/asm/memory.h | 20 ++++++++++++++++++++
>  arch/arm/lib/pbl.lds.S        | 18 ++++++++++++++++++
>  2 files changed, 38 insertions(+)
> 
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 23fbbd8438a1..765b089beb59 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -3,6 +3,9 @@
>  #ifndef __ASM_ARM_MEMORY_H
>  #define __ASM_ARM_MEMORY_H
>  
> +#include <linux/sizes.h>
> +
> +#ifndef __ASSEMBLY__
>  #include <memory.h>
>  
>  #include <linux/const.h>
> @@ -13,4 +16,21 @@ static inline int arm_add_mem_device(const char* name, resource_size_t start,
>  	return barebox_add_memory_bank(name, start, size);
>  }
>  
> +#endif
> +
> +
> +/*
> + * Alignment of barebox PBL segments (e.g. .text, .data).
> + *
> + *  4  B granule:  Same flat rwx mapping for everything
> + *  4 KB granule:  16 level 3 entries, with contiguous bit
> + * 16 KB granule:   4 level 3 entries, without contiguous bit
> + * 64 KB granule:   1 level 3 entry
> + */
> +#ifdef CONFIG_EFI_PAYLOAD
> +#define PBL_SEGMENT_ALIGN		SZ_64K
> +#else
> +#define PBL_SEGMENT_ALIGN		4
> +#endif
> +
>  #endif	/* __ASM_ARM_MEMORY_H */
> diff --git a/arch/arm/lib/pbl.lds.S b/arch/arm/lib/pbl.lds.S
> index cafb27b2d55e..95929d7558bc 100644
> --- a/arch/arm/lib/pbl.lds.S
> +++ b/arch/arm/lib/pbl.lds.S
> @@ -5,6 +5,24 @@
>  #include <asm/barebox.lds.h>
>  #include <asm-generic/memory_layout.h>
>  #include <asm-generic/pointer.h>
> +#include <asm/memory.h>
> +
> +/*
> + * The size of the PE/COFF section that covers the barebox image, which
> + * runs from _stext to _edata, must be a round multiple of the PE/COFF
> + * FileAlignment, which we set to its minimum value of 0x200. '_stext'
> + * itself must be 4 KB aligned, because that's what the adrp instructions
> + * expects, so padding out _edata to a 0x200 aligned boundary should be
> + * sufficient.
> + */
> +PECOFF_FILE_ALIGNMENT = 0x200;
> +
> +#ifdef CONFIG_EFI_STUB
> +#define PECOFF_EDATA_PADDING   \
> +       .pecoff_edata_padding : { BYTE(0); . = ALIGN(PECOFF_FILE_ALIGNMENT); }
> +#else
> +#define PECOFF_EDATA_PADDING
> +#endif
>  
>  #ifdef CONFIG_PBL_RELOCATABLE
>  #define BASE	0x0
> -- 
> 2.39.2
> 
> 
> 

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