[PATCH 3/5] ARM: i.MX8MP: configure PLL3 as noc_io parent

[Ahmad Fatoum]

noc_io is clocked at 24MHz when exiting bootrom, which is a far cry
below the 600MHz it can run at in nominal drive mode.

This doesn't bother us much, because we reconfigure it to 800MHz later
on via assigned-clock-properties, but that frequency is only suitable
when running in overdrive mode (VDD_SOC = 950 mV).

Make switching to nominal mode easier by initializing NOC_IO to
the highest nominal frequency.

Signed-off-by: Ahmad Fatoum <a.fatoum at pengutronix.de>
---
 arch/arm/mach-imx/imx8m.c         | 7 +++++++
 include/mach/imx/imx8m-ccm-regs.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index 211b4f782199..56330cef500c 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -116,6 +116,13 @@ static void __imx8m_early_clock_init(int cpu_type)
 	clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL,
 				    pll3_freq, 25000000UL);
 
+	if (cpu_type == IMX_CPU_IMX8MP) {
+		/* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */
+		imx8m_clock_set_target_val(IMX8M_NOC_IO_CLK_ROOT,
+					   IMX8M_CCM_TARGET_ROOTn_ENABLE |
+					   IMX8M_CCM_TARGET_ROOTn_MUX(2));
+	}
+
 	clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT),
 			IMX8M_CCM_TARGET_ROOTn_MUX(7),
 			IMX8M_CCM_TARGET_ROOTn_MUX(2));
diff --git a/include/mach/imx/imx8m-ccm-regs.h b/include/mach/imx/imx8m-ccm-regs.h
index 29186eb8a7bc..035cd13ed694 100644
--- a/include/mach/imx/imx8m-ccm-regs.h
+++ b/include/mach/imx/imx8m-ccm-regs.h
@@ -22,6 +22,7 @@
  * Applications Processor Reference Manual
  */
 #define IMX8M_ARM_A53_CLK_ROOT		0
+#define IMX8M_NOC_IO_CLK_ROOT           27
 #define IMX8M_DRAM_SEL_CFG		48
 #define IMX8M_DRAM_ALT_CLK_ROOT		64
 #define IMX8M_DRAM_APB_CLK_ROOT		65
-- 
2.39.2