[PATCH v1 2/2] ARM: skov-imx6: Remove unused board variants

[Oleksij Rempel]

From: Sascha Hauer <s.hauer at pengutronix.de>

The board variants 12 and 18 are no longer used. Remove them.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/skov-imx6/lowlevel.c | 136 ---------------------------
 1 file changed, 136 deletions(-)

diff --git a/arch/arm/boards/skov-imx6/lowlevel.c b/arch/arm/boards/skov-imx6/lowlevel.c
index c9a695ced4..16809dd4a6 100644
--- a/arch/arm/boards/skov-imx6/lowlevel.c
+++ b/arch/arm/boards/skov-imx6/lowlevel.c
@@ -28,122 +28,6 @@ static void __udelay(int us)
 
 /* ------------------------------------------------------------------------ */
 
-/*
- * Micron MT41K512M16HA-125 IT:E ->  8 GBit = 64 Meg x 16 x 8 banks
- *
- * Speed Grade   Data Rate (MT/s)  tRCD-tRP-CL   tRCD(ns)  tRP(ns)  CL(ns)
- *    -125          1600            11-11-11      13.75     13.75   13.75
- *               (=800 MHz)
- *
- * Memory configuration used by variant:
- * - "Max Performance", 64 bit data bus, 1066 MHz, 4 GiB memory
- */
-static const struct mx6_ddr3_cfg skov_imx6_cfg_4x512Mb_1066MHz = {
-	.mem_speed = 1066,
-	.density = 8, /* GiBit */
-	.width = 16, /* 16 bit data per device */
-	.banks = 8,
-	.rowaddr = 16, /* 64 k */
-	.coladdr = 10, /* 1 k */
-	.pagesz = 2, /* [kiB] */
-	.trcd = 1375, /* 13.75 ns = 11 clocks @ 1.6 GHz */
-	.trcmin = 4875, /* 48.75 ns = 39 clocks @ 1.6 GHz */
-	.trasmin = 3500, /* 35 ns = 28 clocks @ 1.6 GHz */
-	.SRT = 0,
-};
-
-static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x512Mb_1066MHz = {
-	.dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */
-	.cs_density = 32, /* four 8 GBit devices connected */
-	.ncs = 1, /* one CS line for all devices */
-	.cs1_mirror = 1, /* TODO */
-	.bi_on = 1, /* TODO */
-	.rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */
-	.rtt_wr = 0, /* is LW_EN is 0 in their code */
-	.ralat = 5, /* TODO */
-	.walat = 1, /* TODO */
-	.mif3_mode = 3, /* TODO */
-	.rst_to_cke = 0x23, /* used in their code as well */
-	.sde_to_rst = 0x10, /* used in their code as well */
-	.pd_fast_exit = 0, /* TODO */
-};
-
-static const struct mx6_mmdc_calibration skov_imx6_calib_4x512Mb_1066MHz = {
-	.p0_mpwldectrl0 = 0x001a0017,
-	.p0_mpwldectrl1 = 0x001F001F,
-	.p0_mpdgctrl0 = 0x43040319,
-	.p0_mpdgctrl1 = 0x03040279,
-	.p0_mprddlctl = 0x4d434248,
-	.p0_mpwrdlctl = 0x34424543,
-
-	.p1_mpwldectrl0 = 0x00170027,
-	.p1_mpwldectrl1 = 0x000a001f,
-	.p1_mpdgctrl0 = 0x43040321,
-	.p1_mpdgctrl1 = 0x03030251,
-	.p1_mprddlctl = 0x42413c4d,
-	.p1_mpwrdlctl = 0x49324933,
-};
-
-/* ------------------------------------------------------------------------ */
-
-/*
- * Micron MT41K256M16HA-125 IT:E ->  4 GBit = 32 Meg x 16 x 8 banks
- *
- * Speed Grade   Data Rate (MT/s)  tRCD-tRP-CL   tRCD(ns)  tRP(ns)  CL(ns)
- *    -125          1600            11-11-11      13.75     13.75   13.75
- *               (=800 MHz)
- *
- * Memory configuration used by variant:
- * - "Max Performance", 64 bit data bus, 1066 MHz, 2 GiB memory
- */
-static const struct mx6_ddr3_cfg skov_imx6_cfg_4x256Mb_1066MHz = {
-	.mem_speed = 1066,
-	.density = 4, /* GiBit */
-	.width = 16, /* 16 bit data per device */
-	.banks = 8,
-	.rowaddr = 15, /* 32 k */
-	.coladdr = 10, /* 1 k */
-	.pagesz = 2, /* [kiB] */
-	.trcd = 1375, /* 13.75 ns = 11 clocks @ 1.6 GHz */
-	.trcmin = 4875, /* 48.75 ns = 39 clocks @ 1.6 GHz */
-	.trasmin = 3500, /* 35 ns = 28 clocks @ 1.6 GHz */
-	.SRT = 0,
-};
-
-static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x256Mb_1066MHz = {
-	.dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */
-	.cs_density = 16, /* four 4 GBit devices connected */
-	.ncs = 1, /* one CS line for all devices */
-	.cs1_mirror = 1, /* TODO */
-	.bi_on = 1, /* TODO */
-	.rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */
-	.rtt_wr = 0, /* is LW_EN is 0 in their code */
-	.ralat = 5, /* TODO */
-	.walat = 1, /* TODO */
-	.mif3_mode = 3, /* TODO */
-	.rst_to_cke = 0x23, /* used in their code as well */
-	.sde_to_rst = 0x10, /* used in their code as well */
-	.pd_fast_exit = 0, /* TODO */
-};
-
-static const struct mx6_mmdc_calibration skov_imx6_calib_4x256Mb_1066MHz = {
-	.p0_mpwldectrl0 = 0x001a0017,
-	.p0_mpwldectrl1 = 0x001F001F,
-	.p0_mpdgctrl0 = 0x43040319,
-	.p0_mpdgctrl1 = 0x03040279,
-	.p0_mprddlctl = 0x4d434248,
-	.p0_mpwrdlctl = 0x34424543,
-
-	.p1_mpwldectrl0 = 0x00170027,
-	.p1_mpwldectrl1 = 0x000a001f,
-	.p1_mpdgctrl0 = 0x43040321,
-	.p1_mpdgctrl1 = 0x03030251,
-	.p1_mprddlctl = 0x42413c4d,
-	.p1_mpwrdlctl = 0x49324933,
-};
-
-/* ------------------------------------------------------------------------ */
-
 /*
  * Micron MT41K128M16JT-125 IT:K ->  2 GBit = 16 Meg x 16 x 8 banks
  *
@@ -530,26 +414,6 @@ static void skov_imx6_init(int cpu_type, unsigned board_variant)
 	int instance;
 
 	switch (board_variant) {
-	case 12: /* P2 i.MX6Q, max performance */
-		if (cpu_type != IMX6_CPUTYPE_IMX6Q) {
-			pr_err("Invalid SoC! i.MX6Q expected\n");
-			return;
-		}
-		pr_debug("Initializing a P2 max performance system...\n");
-		spl_imx6q_dram_init(&skov_imx6_sysinfo_4x256Mb_1066MHz,
-					&skov_imx6_calib_4x256Mb_1066MHz,
-					&skov_imx6_cfg_4x256Mb_1066MHz);
-		break;
-	case 18: /* i.MX6Q+ */
-		if (cpu_type != IMX6_CPUTYPE_IMX6Q) {
-			pr_err("Invalid SoC! i.MX6Q expected\n");
-			return;
-		}
-		pr_debug("Initializing board variant 18\n");
-		spl_imx6q_dram_init(&skov_imx6_sysinfo_4x512Mb_1066MHz,
-					&skov_imx6_calib_4x512Mb_1066MHz,
-					&skov_imx6_cfg_4x512Mb_1066MHz);
-		break;
 	case 19: /* i.MX6S "Solo_R512M_F2G" */
 		if (cpu_type != IMX6_CPUTYPE_IMX6S) {
 			pr_err("Invalid SoC! i.MX6S expected\n");
-- 
2.39.2