[PATCH 27/27] ARM: mmu64: Use two level pagetables in early code

[Sascha Hauer]

On Fri, May 12, 2023 at 01:10:08PM +0200, Sascha Hauer wrote:
> So far we used 1GiB sized sections in the early MMU setup. This has
> the disadvantage that we can't use the MMU in early code when we
> require a finer granularity. Rockchip for example keeps TF-A code
> in the lower memory so the code just skipped MMU initialization.
> Also we can't properly map the OP-TEE space at the end of SDRAM non
> executable.
> 
> With this patch we now use two level page tables and can map with 4KiB
> granularity.
> 
> The MMU setup in barebox proper changes as well. Instead of disabling
> the MMU for reconfiguration we can now keep the MMU enabled and just
> add the mappings for SDRAM banks not known to the early code.
> 
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  arch/arm/cpu/mmu_64.c | 97 ++++++++++---------------------------------
>  1 file changed, 21 insertions(+), 76 deletions(-)
> 
> diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
> index 4b75be621d..3f9b52bbdb 100644
> --- a/arch/arm/cpu/mmu_64.c
> +++ b/arch/arm/cpu/mmu_64.c
> @@ -192,37 +193,25 @@ static void mmu_enable(void)
>  void __mmu_init(bool mmu_on)
>  {
>  	struct memory_bank *bank;
> -	unsigned int el;
> -
> -	if (mmu_on)
> -		mmu_disable();
> -
> -	ttb = alloc_pte();
> -	el = current_el();
> -	set_ttbr_tcr_mair(el, (uint64_t)ttb, calc_tcr(el, BITS_PER_VA),
> -			  MEMORY_ATTRIBUTES);
>  
> -	pr_debug("ttb: 0x%p\n", ttb);
> +	reserve_sdram_region("OP-TEE", 0xf0000000 - OPTEE_SIZE, OPTEE_SIZE);

This line shouldn't be here. I only used that for testing.

Sascha

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