[PATCH] ARM: zynq: get ps_clk_rate from dt

[Steffen Trumtrar]

From: "Assmann Kai (BEG/EMS1)" <Kai.Assmann at de.bosch.com>

This adds a barebox-specific binding to overwrite the PS clock
frequency.

Currently the ps_clk_rate is locked to 33.3MHz. Introduce a devicetree
property "ps-clock-frequency" that specifies this clock.

If the property is found, overwrite ps_clk_rate otherwise stay at the
default 33.3MHz

Signed-off-by: Assmann Kai (BEG/MSD-NE2) <Kai.Assmann at de.bosch.com>
Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
---

Notes:
    changes since v1:
     - reword commit message
     - add binding rst
     - change type of ps_clk_frequency

 .../devicetree/bindings/clocks/xlnx,ps7-clkc.rst       | 10 ++++++++++
 drivers/clk/zynq/clkc.c                                |  4 +++-
 2 files changed, 13 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clocks/xlnx,ps7-clkc.rst

diff --git a/Documentation/devicetree/bindings/clocks/xlnx,ps7-clkc.rst b/Documentation/devicetree/bindings/clocks/xlnx,ps7-clkc.rst
new file mode 100644
index 0000000000..523b0cf56e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clocks/xlnx,ps7-clkc.rst
@@ -0,0 +1,10 @@
+Xilinx PS7 clkc
+===============
+
+In addition to the upstream bindings, following properties are understood:
+
+Optional properties:
+
+- ``ps-clock-frequency`` : Overrides the ps clock frequency set by the driver.
+  Per default the clock is set to 33.3MHz. When this property is set, the frequency
+  is overwritten by the devicetree property.
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 1219e25f7a..d6de583e32 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -368,7 +368,7 @@ static int zynq_clock_probe(struct device *dev)
 {
 	struct resource *iores;
 	void __iomem *clk_base;
-	unsigned long ps_clk_rate = 33333330;
+	u32 ps_clk_rate = 33333330;
 	resource_size_t slcr_offset = 0;
 
 	iores = dev_get_resource(dev, IORESOURCE_MEM, 0);
@@ -390,6 +390,8 @@ static int zynq_clock_probe(struct device *dev)
 		slcr_offset = parent_res->start;
 	}
 
+	of_property_read_u32(dev->device_node, "ps-clk-frequency", &ps_clk_rate);
+
 	iores = request_iomem_region(dev_name(dev), iores->start + slcr_offset,
 				     iores->end + slcr_offset);
 	if (IS_ERR(iores))
-- 
2.41.0