[PATCH 14/17] MIPS: pbl_macros: use generic load/store macros in copy_to_link_location

[Denis Orlov]

This may speed up this code a little on MIPS64, however this also allows
us to get rid of unnecessary macro definition there, simplifying the
code a tiny bit.

Signed-off-by: Denis Orlov <denorl2009 at gmail.com>
---
 arch/mips/include/asm/pbl_macros.h | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index ce169a1554..f8629d3f2c 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -120,22 +120,21 @@
 	PTR_SUBU	t2, t1, t0	/* t2 <- size of pbl */
 	PTR_ADDU	a2, a0, t2	/* a2 <- source end address */
 
-#define WSIZE	4
 copy_loop:
 	/* copy from source address [a0] */
-	lw	ta0, WSIZE * 0(a0)
-	lw	ta1, WSIZE * 1(a0)
-	lw	ta2, WSIZE * 2(a0)
-	lw	ta3, WSIZE * 3(a0)
+	LONG_L	ta0, LONGSIZE * 0(a0)
+	LONG_L	ta1, LONGSIZE * 1(a0)
+	LONG_L	ta2, LONGSIZE * 2(a0)
+	LONG_L	ta3, LONGSIZE * 3(a0)
 	/* copy to target address [a1] */
-	sw	ta0, WSIZE * 0(a1)
-	sw	ta1, WSIZE * 1(a1)
-	sw	ta2, WSIZE * 2(a1)
-	sw	ta3, WSIZE * 3(a1)
-	PTR_ADDI	a0, WSIZE * 4
+	LONG_S	ta0, LONGSIZE * 0(a1)
+	LONG_S	ta1, LONGSIZE * 1(a1)
+	LONG_S	ta2, LONGSIZE * 2(a1)
+	LONG_S	ta3, LONGSIZE * 3(a1)
+	PTR_ADDI	a0, LONGSIZE * 4
 	PTR_SUBU	t3, a0, a2
 	blez	t3, copy_loop
-	 PTR_ADDI	a1, WSIZE * 4
+	 PTR_ADDI	a1, LONGSIZE * 4
 
 copy_loop_exit:
 
-- 
2.41.0