[PATCH 3/3] mci: imx-esdhc-pbl: fix prediv setting

[Sascha Hauer]

We use a hardcoded minimum pre_div value of 2. This leads to suboptimal
rates on some SoCs. The pre_div minimum of 2 is required only on one
controller found on the i.MX53, so limit this quirk to this controller
only and use pre_div minimum of 1 for all other controllers.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/mci/imx-esdhc.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index e1d4e3c2d4..d2a590a967 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -21,6 +21,8 @@
 #include <platform_data/mmc-esdhc-imx.h>
 #include <gpio.h>
 #include <of_device.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx53-regs.h>
 
 #include "sdhci.h"
 #include "imx-esdhc.h"
@@ -57,15 +59,11 @@ static void set_sysctl(struct mci_host *mci, u32 clock, bool ddr)
 	if (esdhc_is_layerscape(host))
 		sdhc_clk >>= 1;
 
-	/*
-	 * With eMMC and imx53 (sdhc_clk=200MHz) a pre_div of 1 results in
-	 *	pre_div=1,div=4 (=50MHz)
-	 * which is valid and should work, but somehow doesn't.
-	 * Starting with pre_div=2 gives
-	 *	pre_div=2, div=2 (=50MHz)
-	 * and works fine.
-	 */
-	pre_div = 2;
+	/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+	if (cpu_is_mx53() && host->sdhci.base == (void *)MX53_ESDHC3_BASE_ADDR)
+		pre_div = 2;
+	else
+		pre_div = 1;
 
 	if (sdhc_clk == clock)
 		pre_div = 1;
-- 
2.39.2