[PATCH 4/6] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags

[Sascha Hauer]

On Tue, Sep 13, 2022 at 02:49:52PM +0200, Marco Felsch wrote:
> Use the dedicated scratch register for setting the pbl flags. Each mode
> has it's own scratch register so we are not conflicting with M-mode
> running firmware e.g. OpenSBI. Using the scratch register has two main
> advantages:
>  1st) It can be used in PBL and non-PBL use-case.
>  2nd) It is not affected by the relocation code.
> 
> This commit prepares barebox to add support for the special cache ops
> used by several T-Head CPUs.
> 
> +static inline void riscv_set_flags(unsigned flags)
> +{
> +	switch (flags & RISCV_MODE_MASK) {
> +	case RISCV_S_MODE:
> +		__asm__ volatile("csrw sscratch, %0" : : "r"(flags));
> +		break;
> +	case RISCV_M_MODE:
> +		__asm__ volatile("csrw mscratch, %0" : : "r"(flags));
> +		break;
> +	default:
> +		/* Other modes are not implemented yet */
> +	}

Compilation ends in an error here:

arch/riscv/include/asm/system.h:27:2: error: label at end of compound statement

Sascha

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