[PATCH 0/6] RISC-V Allwinner D1 Support 2nd Stage Support

[Marco Felsch]

Hi,

this small series adds the basic support for the Allwinner sun20i D1
Nezsha board. It is very limited only serial is supported right now.

Patches 1-4 can be applied independently.

Patch 5 may need some more attention since Ahmad told me in person that
not all softcores implementing the vendorid register. Please see the
patch notes on this patch.

Patch 6 adds the support for the D1 board and a detailed description how
to build and flash a bootable image.

Marco Felsch (6):
  RISC-V: cache: fix local_flush_icache_all enabling
  RISC-V: add riscv_vendor_id() support
  RISC-V: import vendorid list from linux
  RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags
  RISC-V: implement cache-management errata for T-Head SoCs
  RISC-V: add Allwinner Sun20i D1 Nezha support

 Documentation/boards/riscv.rst            | 102 +++++++++++++++++
 arch/riscv/Kconfig.socs                   |  16 +++
 arch/riscv/boards/Makefile                |   1 +
 arch/riscv/boards/allwinner-d1/Makefile   |   3 +
 arch/riscv/boards/allwinner-d1/lowlevel.c |  12 ++
 arch/riscv/boot/entry.c                   |   3 +-
 arch/riscv/boot/entry.h                   |   6 +-
 arch/riscv/boot/start.c                   |  13 +--
 arch/riscv/boot/uncompress.c              |   8 +-
 arch/riscv/configs/sun20i_defconfig       | 130 ++++++++++++++++++++++
 arch/riscv/include/asm/cache.h            |  23 +++-
 arch/riscv/include/asm/debug_ll.h         |   5 +
 arch/riscv/include/asm/system.h           |  71 +++++++++---
 arch/riscv/include/asm/vendorid_list.h    |  11 ++
 common/Kconfig                            |   5 +
 images/Makefile.riscv                     |   4 +
 16 files changed, 380 insertions(+), 33 deletions(-)
 create mode 100644 arch/riscv/boards/allwinner-d1/Makefile
 create mode 100644 arch/riscv/boards/allwinner-d1/lowlevel.c
 create mode 100644 arch/riscv/configs/sun20i_defconfig
 create mode 100644 arch/riscv/include/asm/vendorid_list.h

-- 
2.30.2