[PATCH v2 5/7] RISC-V: implement cache-management errata for T-Head SoCs

Marco Felsch m.felsch at pengutronix.de
Wed Oct 5 04:12:12 PDT 2022

Since riscv_vendor_id() can be used from pbl and non-pbl context as well
as from relocated and non-relocated code, we are able to query the
vendor id and add special vendor handlings. This is required since the
T-Head C906 and C910 implement a scheme for handling cache operations
different from the generic Zicbom extension.

While on it replace the 'asm' statement by '__asm__' so we are not
relying on GNU extension.

Signed-off-by: Marco Felsch <m.felsch at pengutronix.de>

please note that I'm aware of the fact that not all RISC-V cores
implementing the vendorid register, which is quirky according the
"privileged architecture" documentation. For such cores I would propose
to extend the pbl-flags by adding a quirks field. Platforms not
supporting the vendorid register can set the quirk within th
lowlevel/pbl code e.g.:

  barebox_riscv_supervisor_entry(DRAM_BASE, SZ_1G, hartid, fdt, RISCV_QUIRK_NO_VENDORID);

This can be parsed by riscv_vendor_id() so in such case the vendorid 0
which is:

3.1.2 Machine Vendor ID Register mvendorid

The mvendorid CSR is a 32-bit read-only register providing the JEDEC
manufacturer ID of the provider of the core. This register must be
readable in any implementation, but a value of 0 can be returned to
indicate the field is not implemented or that this is a non-commercial


 arch/riscv/include/asm/cache.h | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index 6d69ed49bd..c787f89001 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -6,10 +6,29 @@
+#include <asm/vendorid_list.h>
+static inline void thead_local_flush_icache_all(void)
+	/*
+	 * According [1] "13.3 Example of cache settings"
+	 * [1]: https://github.com/T-head-Semi/openc906/blob/main/ \
+	 *	doc/openc906%20datasheet.pd
+	 */
+	__asm__ volatile (".long 0x0100000b" ::: "memory"); /* th.icache.iall */
+	__asm__ volatile (".long 0x01b0000b" ::: "memory"); /* th.sync.is */
 static inline void local_flush_icache_all(void)
-	asm volatile ("fence.i" ::: "memory");
+	switch(riscv_vendor_id()) {
+		thead_local_flush_icache_all();
+		break;
+	default:
+		__asm__ volatile ("fence.i" ::: "memory");
+	}

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