PCIE on LS1021A
Renaud.Barbier at ametek.com
Fri Dec 9 09:31:09 PST 2022
We have added support for the LS1021A in barebox (from v2022.03)
At present neither Linux and barebox are able to probe the PCIE device connected to PE1
The board has a switch fabric connected to PCE1.
Using U-boot we are able to see this device and the NXP bridge
Using barebox we see only the Bridge. Then, it fails on the first read to get the header type from the deivice on bus 1.
We know this driver works on the LS1046A as it can detects a PCI card on the LS1046A-RDB.
Both the LS1021A (32-bit cpu) and LS1046 (64-bit cpu) have their PCIE space to access the device conf, I/O and mem space in 64-bit address space
On the LS1046 I do see access at 0x40.xxxx.xxxx while on the LS1021A, it is only a 32-bit access using the lower 32-bit.
As an experiemnt in U-boot, I have disabled the PCI driver and configured the bridge to access the device.
To my surprise I could see the device not using the 40-bit address. So I am not sure it gets mapped (I send a question to NXP)
=> md 0x24000000
24000000: b86114e4 00100000 02000002 00000000 ..a.............
Doint the same operation on barebox, the data are only
barebox:/ md 0x24000000
24000000: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ................
barebox:/ md 0x4024000000
4024000000: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ................
4024000010: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ................
>From my debugging I can see that the Layerscape PCIE driver use VA address = PA address = 0x24000000
So Is the problem I am seeing an issue with mapping the correct physical address for a 32-bit processor?
If yes, how can I map the 64-bit PA to a 32-bit VA?
More information about the barebox