[PATCH 1/1] ddr: imx8m: Rework ddrphy code and fix DDR-1067 on iMX8MM
sha at pengutronix.de
Fri Oct 1 05:14:12 PDT 2021
On Thu, Sep 23, 2021 at 08:14:46PM -0700, Trent Piepho wrote:
> This code could not decide if it was using speeds in Hz, or MHz, or just
> constants that identify specific speeds.
> Rework it to use symbolic constants for all speeds. Use arrays
> for configurations values for all cases. The DDR DRAM speed constants
> will be the array index, so the linear search for the configuration is
> For iMX8MM type SoCs using the integr PLL the speed DDR-1067 with a 266⅔
> MHz clock will now work.
> The iM8MQ type SSCG PLL SoCs would previously silently program the PLL
> will zero values if a non-supported DDR rate was used. Now they will
> generate an error.
> Note that some PLL tables have entries for speeds that the main entry
> point for the code does not support, so they can't actually ever be
> used. This is not fixed.
> Signed-off-by: Trent Piepho <tpiepho at gmail.com>
> drivers/ddr/imx8m/ddrphy_utils.c | 332 ++++++++++++++-----------------
> 1 file changed, 147 insertions(+), 185 deletions(-)
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