[PATCH] fixup! clocksource: add driver for RISC-V and CLINT timers

[Ahmad Fatoum]

This were wrongly squashed into the commit after.

Signed-off-by: Ahmad Fatoum <ahmad at a3f.at>
---
 arch/riscv/Kconfig                |  1 +
 arch/riscv/dts/erizo.dtsi         |  2 +-
 drivers/clocksource/Kconfig       |  2 +-
 drivers/clocksource/timer-riscv.c | 18 +++++++++++++++++-
 4 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ce338e3f1f95..c0583f31536b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -32,6 +32,7 @@ config MACH_ERIZO
 	select HAS_NMON
 	select USE_COMPRESSED_DTB
 	select RISCV_M_MODE
+	select RISCV_TIMER
 
 config MACH_VIRT
 	bool "virt family"
diff --git a/arch/riscv/dts/erizo.dtsi b/arch/riscv/dts/erizo.dtsi
index 07534798ac75..e854a48ae55c 100644
--- a/arch/riscv/dts/erizo.dtsi
+++ b/arch/riscv/dts/erizo.dtsi
@@ -22,7 +22,7 @@ fixed-clock
 
 		cpu at 0 {
 			device_type = "cpu";
-			compatible = "cliffordwolf,picorv32";
+			compatible = "cliffordwolf,picorv32", "riscv";
 			clocks = <&ref_clk>;
 			reg = <0>;
 		};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2d8f5113ad8d..7bc69afd7820 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -101,7 +101,7 @@ config CLOCKSOURCE_TI_32K
 
 config RISCV_TIMER
 	bool "Timer for the RISC-V platform" if COMPILE_TEST
-	depends on RISCV && RISCV_SBI
+	depends on RISCV
 	help
 	  This enables the per-hart timer built into all RISC-V systems, which
 	  is accessed via both the SBI and the rdcycle instruction.  This is
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 637285fd78a7..eb5ba2d8c226 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -13,7 +13,7 @@
 #include <asm/timer.h>
 #include <asm/csr.h>
 
-static u64 notrace riscv_timer_get_count(void)
+static u64 notrace riscv_timer_get_count_sbi(void)
 {
 	__maybe_unused u32 hi, lo;
 
@@ -28,6 +28,22 @@ static u64 notrace riscv_timer_get_count(void)
 	return ((u64)hi << 32) | lo;
 }
 
+static u64 notrace riscv_timer_get_count_rdcycle(void)
+{
+	u64 ticks;
+	asm volatile("rdcycle %0" : "=r" (ticks));
+
+	return ticks;
+}
+
+static u64 notrace riscv_timer_get_count(void)
+{
+	if (IS_ENABLED(CONFIG_RISCV_SBI))
+		return riscv_timer_get_count_sbi();
+	else
+		return riscv_timer_get_count_rdcycle();
+}
+
 static struct clocksource riscv_clocksource = {
 	.read		= riscv_timer_get_count,
 	.mask		= CLOCKSOURCE_MASK(64),
-- 
2.30.0