[PATCH v3 13/21] RISC-V: implement PBL image header

[Ahmad Fatoum]

We'll adopt the RISC-V Linux kernel image header structure for the
barebox images as well. The __barebox_riscv_header() macro implementing
it can customize some fields to allow differentiating between barebox
and kernel images. It will be used in follow-up commits to implement
the entry points of both the erizo image and the generic DT image.

Signed-off-by: Ahmad Fatoum <a.fatoum at pengutronix.de>
---
 arch/riscv/include/asm/barebox-riscv-head.h | 36 ++++++++++++
 arch/riscv/include/asm/image.h              | 65 +++++++++++++++++++++
 2 files changed, 101 insertions(+)
 create mode 100644 arch/riscv/include/asm/barebox-riscv-head.h
 create mode 100644 arch/riscv/include/asm/image.h

diff --git a/arch/riscv/include/asm/barebox-riscv-head.h b/arch/riscv/include/asm/barebox-riscv-head.h
new file mode 100644
index 000000000000..f681ec8bcee6
--- /dev/null
+++ b/arch/riscv/include/asm/barebox-riscv-head.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (c) 2021 Ahmad Fatoum, Pengutronix */
+
+#ifndef __ASM_RISCV_HEAD_H
+#define __ASM_RISCV_HEAD_H
+
+#include <linux/kernel.h>
+#include <asm/image.h>
+
+#define ____barebox_riscv_header(instr, load_offset, version, magic1, magic2)         \
+	__asm__ __volatile__ (                                                        \
+		instr "\n"                     /* code0 */                            \
+		"j 1f\n"                       /* code1 */                            \
+		".balign 8\n"                                                         \
+		".dword " #load_offset "\n"    /* Image load offset from RAM start */ \
+		".dword _barebox_image_size\n" /* Effective Image size */             \
+		".dword 0\n"                   /* Kernel flags */                     \
+		".word " #version "\n"         /* version */                          \
+		".word 0\n"                    /* reserved */                         \
+		".dword 0\n"                   /* reserved */                         \
+		".asciz \"" magic1 "\"\n"      /* magic 1 */                          \
+		".balign 8\n"                                                         \
+		".ascii \"" magic2 "\"\n"      /* magic 2 */                          \
+		".word 0\n"                    /* reserved (PE-COFF offset) */        \
+		"1:\n"                                                                \
+	)
+
+#define __barebox_riscv_header(instr, load_offset, version, magic1, magic2) \
+        ____barebox_riscv_header(instr, load_offset, version, magic1, magic2)
+
+#ifndef __barebox_riscv_head
+#define __barebox_riscv_head() \
+	__barebox_riscv_header("nop", 0x55555555FFFFFFFF, 0x0, "barebox", "RSCV")
+#endif
+
+#endif /* __ASM_RISCV_HEAD_H */
diff --git a/arch/riscv/include/asm/image.h b/arch/riscv/include/asm/image.h
new file mode 100644
index 000000000000..e0b319af3681
--- /dev/null
+++ b/arch/riscv/include/asm/image.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _ASM_RISCV_IMAGE_H
+#define _ASM_RISCV_IMAGE_H
+
+#define RISCV_IMAGE_MAGIC	"RISCV\0\0\0"
+#define RISCV_IMAGE_MAGIC2	"RSC\x05"
+
+#define RISCV_IMAGE_FLAG_BE_SHIFT	0
+#define RISCV_IMAGE_FLAG_BE_MASK	0x1
+
+#define RISCV_IMAGE_FLAG_LE		0
+#define RISCV_IMAGE_FLAG_BE		1
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#error conversion of header fields to LE not yet implemented
+#else
+#define __HEAD_FLAG_BE		RISCV_IMAGE_FLAG_LE
+#endif
+
+#define __HEAD_FLAG(field)	(__HEAD_FLAG_##field << \
+				RISCV_IMAGE_FLAG_##field##_SHIFT)
+
+#define __HEAD_FLAGS		(__HEAD_FLAG(BE))
+
+#define RISCV_HEADER_VERSION_MAJOR 0
+#define RISCV_HEADER_VERSION_MINOR 2
+
+#define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \
+			      RISCV_HEADER_VERSION_MINOR)
+
+#ifndef __ASSEMBLY__
+/**
+ * struct riscv_image_header - riscv kernel image header
+ * @code0:		Executable code
+ * @code1:		Executable code
+ * @text_offset:	Image load offset (little endian)
+ * @image_size:		Effective Image size (little endian)
+ * @flags:		kernel flags (little endian)
+ * @version:		version
+ * @res1:		reserved
+ * @res2:		reserved
+ * @magic:		Magic number (RISC-V specific; deprecated)
+ * @magic2:		Magic number 2 (to match the ARM64 'magic' field pos)
+ * @res3:		reserved (will be used for PE COFF offset)
+ *
+ * The intention is for this header format to be shared between multiple
+ * architectures to avoid a proliferation of image header formats.
+ */
+
+struct riscv_image_header {
+	u32 code0;
+	u32 code1;
+	u64 text_offset;
+	u64 image_size;
+	u64 flags;
+	u32 version;
+	u32 res1;
+	u64 res2;
+	u64 magic;
+	u32 magic2;
+	u32 res3;
+};
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_RISCV_IMAGE_H */
-- 
2.29.2