[PATCH v2 14/20] RISC-V: erizo: migrate to PBL

[Antony Pavlov]

On Tue, 16 Mar 2021 09:04:59 +0100
Ahmad Fatoum <a.fatoum at pengutronix.de> wrote:

> We now have everything in place to migrate erizo to PBL.
> As currently, this is the only board, we can drop all non-PBL support
> in the same go.
...
> diff --git a/arch/riscv/boards/erizo/lowlevel.c b/arch/riscv/boards/erizo/lowlevel.c
> index f9c640c1123f..d9edb530b746 100644
> --- a/arch/riscv/boards/erizo/lowlevel.c
> +++ b/arch/riscv/boards/erizo/lowlevel.c
> @@ -1,35 +1,18 @@
>  // SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (C) 2016 Antony Pavlov <antonynpavlov at gmail.com>
> - *
> - * This file is part of barebox.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - *
> - */
>  
>  #include <common.h>
> -#include <memory.h>
> -#include <asm-generic/memory_layout.h>
> -#include <asm/sections.h>
> +#include <asm/barebox-riscv.h>
> +#include <debug_ll.h>
>  
> -void main_entry(void);
> -
> -/**
> - * Called plainly from assembler code
> - *
> - * @note The C environment isn't initialized yet
> - */
> -void main_entry(void)
> +ENTRY_FUNCTION(start_erizo_generic, a0, a1, a2)
>  {
> -	/* clear the BSS first */
> -	memset(__bss_start, 0x00, __bss_stop - __bss_start);
> +	extern char __dtb_z_erizo_generic_start[];
> +
> +	debug_ll_ns16550_init();
> +	putc_ll('>');
>  
> -	mem_malloc_init((void *)MALLOC_BASE,
> -			(void *)(MALLOC_BASE + MALLOC_SIZE - 1));
> +	/* On POR, we are running from read-only memory here. */
>  
> -	start_barebox();
> +	barebox_riscv_entry(0x80000000, SZ_8M,
> +			    __dtb_z_erizo_generic_start + get_runtime_offset());
>  }


Let's see first instructions of resulting barebox-erizo-generic.img image:

  barebox$ xxd -l 16 -e -g 4 ./images/barebox-erizo-generic.img
  00000000: ff010113 00112623 900007b7 08700713  ....#&........p.

one can disassembly it:

  barebox$ riscv64-linux-gnu-objdump -D images/start_erizo_generic.pbl | head -n 9

  images/start_erizo_generic.pbl:     file format elf32-littleriscv


  Disassembly of section .text:

  00000000 <start_erizo_generic>:
     0:	ff010113          	addi	sp,sp,-16
     4:	00112623          	sw	ra,12(sp)


In general case 'sp' is in indeterminate state at start.
But despite this we use 'sp'-based address
for storing 'ra' register in memory! (sw ra,12(sp))

This behaviour can be fixed with adding __naked to ENTRY_FUNCTION macro definition:

--- a/arch/riscv/include/asm/barebox-riscv.h
+++ b/arch/riscv/include/asm/barebox-riscv.h
@@ -78,7 +78,7 @@ static inline unsigned long riscv_mem_barebox_image(unsigned long membase,
 
 #define ENTRY_FUNCTION(name, arg0, arg1, arg2)         \
        void name (ulong a0, ulong a1, ulong a2);       \
-       void __section(.text_head_entry_##name) name (ulong a0, ulong a1, ulong a2)
+       void __section(.text_head_entry_##name) __naked name (ulong a0, ulong a1, ulong a2)
 
 /*
  * When using compressed images in conjunction with relocatable images

-- 
Best regards,
  Antony Pavlov