[PATCH v3 2/2] arm: rk3568-evb1: add support for Rockchip SARADC

[Michael Riesch]

Signed-off-by: Michael Riesch <michael.riesch at wolfvision.net>
---
v3:
- no changes

v2:
- add initial version

 arch/arm/dts/rk3568-evb1-v10.dts |  6 +++++-
 arch/arm/dts/rk3568.dtsi         | 12 ++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts
index 91e234419..c22692116 100644
--- a/arch/arm/dts/rk3568-evb1-v10.dts
+++ b/arch/arm/dts/rk3568-evb1-v10.dts
@@ -456,6 +456,11 @@
 	};
 };

+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
 &sdhci {
 	bus-width = <8>;
 	max-frequency = <200000000>;
@@ -579,4 +584,3 @@
 &combphy1_usq {
 	status = "okay";
 };
-
diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
index 3baaec3a8..0f19d3f0c 100644
--- a/arch/arm/dts/rk3568.dtsi
+++ b/arch/arm/dts/rk3568.dtsi
@@ -1030,6 +1030,18 @@
 		status = "disabled";
 	};

+	saradc: saradc at fe720000 {
+		compatible = "rockchip,rk3568-saradc";
+		reg = <0x0 0xfe720000 0x0 0x100>;
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_P_SARADC>;
+		reset-names = "saradc-apb";
+		#io-channel-cells = <1>;
+		status = "disabled";
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3568-pinctrl";
 		rockchip,grf = <&grf>;
--
2.20.1